/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_dpp_cm.c | 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name 119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap() 121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap() 214 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix() 216 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix() 261 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field() 263 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field() 265 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field() 267 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field() 270 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field() [all …]
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D | dcn10_dpp.c | 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 509 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) in dpp1_dppclk_control() 564 const struct dcn_dpp_mask *tf_mask) in dpp1_construct() argument 574 dpp->tf_mask = tf_mask; in dpp1_construct()
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D | dcn10_dpp_dscl.c | 51 dpp->tf_shift->field_name, dpp->tf_mask->field_name 364 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, in dpp1_dscl_set_scl_filter()
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D | dcn10_resource.c | 362 static const struct dcn_dpp_mask tf_mask = { variable 587 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
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D | dcn10_dpp.h | 1361 const struct dcn_dpp_mask *tf_mask; member 1523 const struct dcn_dpp_mask *tf_mask);
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_dpp_cm.c | 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 177 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field() 179 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field() 182 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field() 184 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field() 186 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field() 188 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field() 191 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field() 193 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field() 195 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field() [all …]
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D | dcn30_dpp.c | 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; in dpp3_program_post_csc() 103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; in dpp3_program_post_csc() 638 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field() 640 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn3_dpp_cm_get_reg_field() 642 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field() 644 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn3_dpp_cm_get_reg_field() 647 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field() 649 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field() 651 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field() [all …]
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D | dcn30_dpp.h | 565 const struct dcn3_dpp_mask *tf_mask; member 584 const struct dcn3_dpp_mask *tf_mask);
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn32/ |
D | dcn32_dpp.c | 151 const struct dcn3_dpp_mask *tf_mask) in dpp32_construct() argument 161 dpp->tf_mask = tf_mask; in dpp32_construct()
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D | dcn32_dpp.h | 36 const struct dcn3_dpp_mask *tf_mask);
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_dpp_cm.c | 47 dpp->tf_shift->field_name, dpp->tf_mask->field_name 190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap() 192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap() 285 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp2_program_input_csc() 287 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp2_program_input_csc() 363 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field() 365 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field() 367 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field() 369 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field() 372 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field() [all …]
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D | dcn20_dpp.c | 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 409 const struct dcn2_dpp_mask *tf_mask) in dpp2_construct() argument 419 dpp->tf_mask = tf_mask; in dpp2_construct()
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D | dcn20_dpp.h | 683 const struct dcn2_dpp_mask *tf_mask; member 773 const struct dcn2_dpp_mask *tf_mask);
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn201/ |
D | dcn201_dpp.h | 62 const struct dcn201_dpp_mask *tf_mask; member 81 const struct dcn201_dpp_mask *tf_mask);
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D | dcn201_dpp.c | 42 dpp->tf_shift->field_name, dpp->tf_mask->field_name 291 const struct dcn201_dpp_mask *tf_mask) in dpp201_construct() argument 301 dpp->tf_mask = tf_mask; in dpp201_construct()
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D | dcn201_resource.c | 479 static const struct dcn201_dpp_mask tf_mask = { variable 636 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn302/ |
D | dcn302_resource.c | 531 static const struct dcn3_dpp_mask tf_mask = { variable 542 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn303/ |
D | dcn303_resource.c | 491 static const struct dcn3_dpp_mask tf_mask = { variable 502 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn301/ |
D | dcn301_resource.c | 417 static const struct dcn3_dpp_mask tf_mask = { variable 720 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn21/ |
D | dcn21_resource.c | 447 static const struct dcn2_dpp_mask tf_mask = { variable 510 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn316/ |
D | dcn316_resource.c | 487 static const struct dcn3_dpp_mask tf_mask = { variable 918 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn314/ |
D | dcn314_resource.c | 496 static const struct dcn3_dpp_mask tf_mask = { variable 974 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn315/ |
D | dcn315_resource.c | 494 static const struct dcn3_dpp_mask tf_mask = { variable 922 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn321/ |
D | dcn321_resource.c | 372 static const struct dcn3_dpp_mask tf_mask = { variable 930 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn321_dpp_create()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn31/ |
D | dcn31_resource.c | 491 static const struct dcn3_dpp_mask tf_mask = { variable 924 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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