Searched refs:socfpgaclk (Results 1 – 9 of 9) sorted by relevance
24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local27 if (socfpgaclk->fixed_div) { in socfpga_gate_clk_recalc_rate()28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()29 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()40 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_dbg_clk_recalc_rate() local43 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()44 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_dbg_clk_recalc_rate()53 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_get_parent() local[all …]
21 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in n5x_clk_peri_c_clk_recalc_rate() local23 unsigned long shift = socfpgaclk->shift; in n5x_clk_peri_c_clk_recalc_rate()26 val = readl(socfpgaclk->hw.reg); in n5x_clk_peri_c_clk_recalc_rate()36 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_peri_c_clk_recalc_rate() local40 val = readl(socfpgaclk->hw.reg); in clk_peri_c_clk_recalc_rate()50 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_peri_cnt_clk_recalc_rate() local53 if (socfpgaclk->fixed_div) { in clk_peri_cnt_clk_recalc_rate()54 div = socfpgaclk->fixed_div; in clk_peri_cnt_clk_recalc_rate()56 if (socfpgaclk->hw.reg) in clk_peri_cnt_clk_recalc_rate()57 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_peri_cnt_clk_recalc_rate()[all …]
43 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in n5x_clk_pll_recalc_rate() local48 reg = readl(socfpgaclk->hw.reg + 0x8); in n5x_clk_pll_recalc_rate()64 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in agilex_clk_pll_recalc_rate() local69 reg = readl(socfpgaclk->hw.reg); in agilex_clk_pll_recalc_rate()75 reg = readl(socfpgaclk->hw.reg + 0x24); in agilex_clk_pll_recalc_rate()85 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local92 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()99 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()109 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_boot_clk_recalc_rate() local112 div = ((readl(socfpgaclk->hw.reg) & in clk_boot_clk_recalc_rate()[all …]
23 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local26 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()27 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()30 div &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()33 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_periclk_recalc_rate()41 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_get_parent() local45 clk_src = readl(socfpgaclk->hw.reg); in clk_periclk_get_parent()
90 static u32 socfpga_clk_get_div(struct socfpga_gate_clk *socfpgaclk) in socfpga_clk_get_div() argument94 if (socfpgaclk->fixed_div) in socfpga_clk_get_div()95 div = socfpgaclk->fixed_div; in socfpga_clk_get_div()96 else if (socfpgaclk->div_reg) { in socfpga_clk_get_div()97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_get_div()98 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_clk_get_div()100 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_get_div()112 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_recalc_rate() local113 u32 div = socfpga_clk_get_div(socfpgaclk); in socfpga_clk_recalc_rate()122 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_determine_rate() local[all …]
20 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local23 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()24 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()28 val &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()31 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); in clk_periclk_recalc_rate()
24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local27 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
41 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()61 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
37 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()52 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()