| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dpp_cm.c | 118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
213 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
215 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
260 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
262 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
264 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
266 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
269 reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
271 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; in dpp1_cm_get_reg_field()
[all …]
|
| D | dcn10_cm_common.h | 70 struct xfer_func_shift shifts; member
85 struct cm_color_matrix_shift shifts; member
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dwb_cm.c | 52 reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
54 reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
57 reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
59 reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
61 reg->shifts.exp_region1_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
63 reg->shifts.exp_region1_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
66 reg->shifts.field_region_end = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
68 reg->shifts.field_region_end_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
70 reg->shifts.field_region_end_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
72 reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in dwb3_get_reg_field_ogam()
[all …]
|
| D | dcn30_dpp_cm.c | 176 reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
178 reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
181 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
183 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
185 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
187 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
190 reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
192 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
194 reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
196 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; in dpp3_gamcor_reg_field()
[all …]
|
| D | dcn30_mpc.c | 179 reg->shifts.field_region_start_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
181 reg->shifts.field_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
184 reg->shifts.exp_region0_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field()
186 reg->shifts.exp_region0_num_segments = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
188 reg->shifts.exp_region1_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc3_ogam_get_reg_field()
190 reg->shifts.exp_region1_num_segments = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
193 reg->shifts.field_region_end = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field()
195 reg->shifts.field_region_end_slope = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc3_ogam_get_reg_field()
197 reg->shifts.field_region_end_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc3_ogam_get_reg_field()
199 reg->shifts.field_region_linear_slope = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in mpc3_ogam_get_reg_field()
[all …]
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_i2c_hw.c | 41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
621 const struct dce_i2c_shift *shifts, in dce_i2c_hw_construct() argument
628 dce_i2c_hw->shifts = shifts; in dce_i2c_hw_construct()
644 const struct dce_i2c_shift *shifts, in dce100_i2c_hw_construct() argument
651 shifts, in dce100_i2c_hw_construct()
661 const struct dce_i2c_shift *shifts, in dce112_i2c_hw_construct() argument
668 shifts, in dce112_i2c_hw_construct()
678 const struct dce_i2c_shift *shifts, in dcn1_i2c_hw_construct() argument
685 shifts, in dcn1_i2c_hw_construct()
695 const struct dce_i2c_shift *shifts, in dcn2_i2c_hw_construct() argument
[all …]
|
| D | dce_i2c_hw.h | 291 const struct dce_i2c_shift *shifts; member
300 const struct dce_i2c_shift *shifts,
308 const struct dce_i2c_shift *shifts,
316 const struct dce_i2c_shift *shifts,
324 const struct dce_i2c_shift *shifts,
332 const struct dce_i2c_shift *shifts,
|
| D | dce_audio.h | 143 const struct dce_audio_shift *shifts; member
151 const struct dce_audio_shift *shifts,
159 const struct dce_audio_shift *shifts,
|
| D | dce_audio.c | 44 aud->shifts->field_name, aud->masks->field_name
1051 const struct dce_audio_shift *shifts, in dce_audio_create() argument
1067 audio->shifts = shifts; in dce_audio_create()
1077 const struct dce_audio_shift *shifts, in dce60_audio_create() argument
1093 audio->shifts = shifts; in dce60_audio_create()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.c | 164 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_output_csc()
166 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_output_csc()
222 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
224 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
250 reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
252 reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
254 reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
256 reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
258 reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
260 reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field()
[all …]
|
| D | dcn20_dpp_cm.c | 189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
284 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp2_program_input_csc()
286 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; in dpp2_program_input_csc()
362 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
364 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
366 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
368 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
371 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
373 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
[all …]
|
| /linux-6.6.21/drivers/net/dsa/microchip/ |
| D | ksz8795.c | 415 const u8 *shifts; in ksz8_r_dyn_mac_table() local
422 shifts = dev->info->shifts; in ksz8_r_dyn_mac_table()
448 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; in ksz8_r_dyn_mac_table()
450 shifts[DYNAMIC_MAC_ENTRIES]; in ksz8_r_dyn_mac_table()
454 shifts[DYNAMIC_MAC_FID]; in ksz8_r_dyn_mac_table()
456 shifts[DYNAMIC_MAC_SRC_PORT]; in ksz8_r_dyn_mac_table()
458 shifts[DYNAMIC_MAC_TIMESTAMP]; in ksz8_r_dyn_mac_table()
478 const u8 *shifts; in ksz8_r_sta_mac_table() local
483 shifts = dev->info->shifts; in ksz8_r_sta_mac_table()
507 shifts[STATIC_MAC_FWD_PORTS]; in ksz8_r_sta_mac_table()
[all …]
|
| D | ksz9477.c | 671 const u8 *shifts; in ksz9477_mdb_add() local
678 shifts = dev->info->shifts; in ksz9477_mdb_add()
689 data = (index << shifts[ALU_STAT_INDEX]) | in ksz9477_mdb_add()
734 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; in ksz9477_mdb_add()
750 const u8 *shifts; in ksz9477_mdb_del() local
757 shifts = dev->info->shifts; in ksz9477_mdb_del()
768 data = (index << shifts[ALU_STAT_INDEX]) | in ksz9477_mdb_del()
811 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; in ksz9477_mdb_del()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_hubbub.c | 38 hubbub1->shifts->field_name, hubbub1->masks->field_name
48 hubbub1->shifts->field_name, hubbub1->masks->field_name
78 hubbub3->shifts = hubbub_shift; in hubbub301_construct()
|
| /linux-6.6.21/drivers/clk/starfive/ |
| D | clk-starfive-jh7110-pll.c | 108 } shifts; member
127 .shifts = { \
285 ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd; in jh7110_pll_regvals_get()
286 ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd; in jh7110_pll_regvals_get()
289 ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv; in jh7110_pll_regvals_get()
380 (u32)val->mode << info->shifts.dacpd); in jh7110_pll_set_rate()
382 (u32)val->mode << info->shifts.dsmpd); in jh7110_pll_set_rate()
386 val->fbdiv << info->shifts.fbdiv); in jh7110_pll_set_rate()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_hubbub.c | 41 hubbub1->shifts->field_name, hubbub1->masks->field_name
51 hubbub1->shifts->field_name, hubbub1->masks->field_name
102 hubbub->shifts = hubbub_shift; in hubbub201_construct()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| D | hw_factory_dcn10.c | 156 generic->shifts = &generic_shift[en]; in define_generic_registers()
181 ddc->shifts = &ddc_shift; in define_ddc_registers()
191 hpd->shifts = &hpd_shift; in define_hpd_registers()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| D | hw_factory_dcn21.c | 164 generic->shifts = &generic_shift[en]; in define_generic_registers()
189 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
199 hpd->shifts = &hpd_shift; in define_hpd_registers()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| D | hw_factory_dcn32.c | 197 generic->shifts = &generic_shift[en]; in define_generic_registers()
222 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
232 hpd->shifts = &hpd_shift; in define_hpd_registers()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| D | hw_factory_dcn20.c | 201 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
211 hpd->shifts = &hpd_shift; in define_hpd_registers()
221 generic->shifts = &generic_shift[en]; in define_generic_registers()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| D | hw_factory_dcn30.c | 193 generic->shifts = &generic_shift[en]; in define_generic_registers()
218 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
228 hpd->shifts = &hpd_shift; in define_hpd_registers()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| D | hw_factory_dcn315.c | 185 generic->shifts = &generic_shift[en]; in define_generic_registers()
210 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
220 hpd->shifts = &hpd_shift; in define_hpd_registers()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| D | hw_factory_dce110.c | 132 ddc->shifts = &ddc_shift; in define_ddc_registers()
142 hpd->shifts = &hpd_shift; in define_hpd_registers()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dce60/ |
| D | hw_factory_dce60.c | 136 ddc->shifts = &ddc_shift; in define_ddc_registers()
146 hpd->shifts = &hpd_shift; in define_hpd_registers()
|
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| D | hw_factory_dce80.c | 136 ddc->shifts = &ddc_shift; in define_ddc_registers()
146 hpd->shifts = &hpd_shift; in define_hpd_registers()
|