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Searched refs:shared_dpll (Results 1 – 10 of 10) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c116 struct intel_shared_dpll_state *shared_dpll) in intel_atomic_duplicate_dpll_state() argument
124 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
139 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
142 return state->shared_dpll; in intel_atomic_get_shared_dpll_state()
225 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll()
271 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll()
315 struct intel_shared_dpll_state *shared_dpll; in intel_find_shared_dpll() local
318 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_find_shared_dpll()
326 if (shared_dpll[i].pipe_mask == 0) { in intel_find_shared_dpll()
333 &shared_dpll[i].hw_state, in intel_find_shared_dpll()
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Dintel_pch_display.c251 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); in ilk_enable_pch_transcoder()
381 if (crtc_state->shared_dpll == in ilk_pch_enable()
524 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id); in ilk_pch_get_config()
525 pll = crtc_state->shared_dpll; in ilk_pch_get_config()
Dintel_modeset_setup.c92 if (crtc_state->shared_dpll) in intel_crtc_disable_noatomic_begin()
94 crtc_state->shared_dpll, in intel_crtc_disable_noatomic_begin()
95 &crtc_state->shared_dpll->state); in intel_crtc_disable_noatomic_begin()
555 crtc_state->shared_dpll && in has_bogus_dpll_config()
Dintel_ddi.c263 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
1524 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in adls_ddi_enable_clock()
1568 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in rkl_ddi_enable_clock()
1612 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in dg1_ddi_enable_clock()
1678 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_combo_enable_clock()
1722 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in jsl_ddi_tc_enable_clock()
1765 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_enable_clock()
1873 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in skl_ddi_enable_clock()
1941 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in hsw_ddi_enable_clock()
3845 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
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Dintel_display.c1189 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; in intel_encoders_update_prepare()
1505 if (crtc_state->shared_dpll) in icl_ddi_bigjoiner_pre_enable()
1559 if (new_crtc_state->shared_dpll) in hsw_crtc_enable()
1863 if (crtc_state->shared_dpll) in get_crtc_power_domains()
2907 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
3302 pipe_config->shared_dpll = NULL; in ilk_get_pipe_config()
3701 pipe_config->shared_dpll = NULL; in hsw_get_pipe_config()
4570 saved_state->shared_dpll = slave_crtc_state->shared_dpll; in copy_bigjoiner_crtc_state_modeset()
4625 saved_state->shared_dpll = crtc_state->shared_dpll; in intel_crtc_prepare_cleared_state()
5314 PIPE_CONF_CHECK_P(shared_dpll); in intel_pipe_config_compare()
Dintel_display_types.h663 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; member
1169 struct intel_shared_dpll *shared_dpll; member
Dintel_lvds.c247 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll); in intel_pre_enable_lvds()
Dintel_fdi.c784 drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); in hsw_fdi_link_train()
Dintel_dpll.c1530 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); in intel_dpll_crtc_get_shared_dpll()
1532 if (!crtc_state->hw.enable || crtc_state->shared_dpll) in intel_dpll_crtc_get_shared_dpll()
Dicl_dsi.c654 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()