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Searched refs:set_hard_min_dcfclk_by_freq (Results 1 – 4 of 4) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c265 pp_smu->set_hard_min_dcfclk_by_freq && in rv1_update_clocks()
268 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
285 pp_smu->set_hard_min_dcfclk_by_freq && in rv1_update_clocks()
288 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/
Ddm_pp_smu.h118 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz); member
178 enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz); member
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c264 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
/linux-6.6.21/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c768 funcs->rv_funcs.set_hard_min_dcfclk_by_freq = in dm_pp_get_funcs()
777 funcs->nv_funcs.set_hard_min_dcfclk_by_freq = in dm_pp_get_funcs()