1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_debug_h__ 8 #define __iwl_fw_api_debug_h__ 9 10 /** 11 * enum iwl_debug_cmds - debug commands 12 */ 13 enum iwl_debug_cmds { 14 /** 15 * @LMAC_RD_WR: 16 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 17 * &struct iwl_dbg_mem_access_rsp 18 */ 19 LMAC_RD_WR = 0x0, 20 /** 21 * @UMAC_RD_WR: 22 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 23 * &struct iwl_dbg_mem_access_rsp 24 */ 25 UMAC_RD_WR = 0x1, 26 /** 27 * @HOST_EVENT_CFG: 28 * updates the enabled event severities 29 * &struct iwl_dbg_host_event_cfg_cmd 30 */ 31 HOST_EVENT_CFG = 0x3, 32 /** 33 * @INVALID_WR_PTR_CMD: invalid write pointer, set in the TFD 34 * when it's not in use 35 */ 36 INVALID_WR_PTR_CMD = 0x6, 37 /** 38 * @DBGC_SUSPEND_RESUME: 39 * DBGC suspend/resume commad. Uses a single dword as data: 40 * 0 - resume DBGC recording 41 * 1 - suspend DBGC recording 42 */ 43 DBGC_SUSPEND_RESUME = 0x7, 44 /** 45 * @BUFFER_ALLOCATION: 46 * passes DRAM buffers to a DBGC 47 * &struct iwl_buf_alloc_cmd 48 */ 49 BUFFER_ALLOCATION = 0x8, 50 /** 51 * @GET_TAS_STATUS: 52 * sends command to fw to get TAS status 53 * the response is &struct iwl_mvm_tas_status_resp 54 */ 55 GET_TAS_STATUS = 0xA, 56 /** 57 * @FW_DUMP_COMPLETE_CMD: 58 * sends command to fw once dump collection completed 59 * &struct iwl_dbg_dump_complete_cmd 60 */ 61 FW_DUMP_COMPLETE_CMD = 0xB, 62 /** 63 * @MFU_ASSERT_DUMP_NTF: 64 * &struct iwl_mfu_assert_dump_notif 65 */ 66 MFU_ASSERT_DUMP_NTF = 0xFE, 67 }; 68 69 /* Error response/notification */ 70 enum { 71 FW_ERR_UNKNOWN_CMD = 0x0, 72 FW_ERR_INVALID_CMD_PARAM = 0x1, 73 FW_ERR_SERVICE = 0x2, 74 FW_ERR_ARC_MEMORY = 0x3, 75 FW_ERR_ARC_CODE = 0x4, 76 FW_ERR_WATCH_DOG = 0x5, 77 FW_ERR_WEP_GRP_KEY_INDX = 0x10, 78 FW_ERR_WEP_KEY_SIZE = 0x11, 79 FW_ERR_OBSOLETE_FUNC = 0x12, 80 FW_ERR_UNEXPECTED = 0xFE, 81 FW_ERR_FATAL = 0xFF 82 }; 83 84 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations 85 * dbgc suspend resume command operations 86 * @DBGC_RESUME_CMD: resume dbgc recording 87 * @DBGC_SUSPEND_CMD: stop dbgc recording 88 */ 89 enum iwl_dbg_suspend_resume_cmds { 90 DBGC_RESUME_CMD, 91 DBGC_SUSPEND_CMD, 92 }; 93 94 /** 95 * struct iwl_error_resp - FW error indication 96 * ( REPLY_ERROR = 0x2 ) 97 * @error_type: one of FW_ERR_* 98 * @cmd_id: the command ID for which the error occurred 99 * @reserved1: reserved 100 * @bad_cmd_seq_num: sequence number of the erroneous command 101 * @error_service: which service created the error, applicable only if 102 * error_type = 2, otherwise 0 103 * @timestamp: TSF in usecs. 104 */ 105 struct iwl_error_resp { 106 __le32 error_type; 107 u8 cmd_id; 108 u8 reserved1; 109 __le16 bad_cmd_seq_num; 110 __le32 error_service; 111 __le64 timestamp; 112 } __packed; 113 114 #define TX_FIFO_MAX_NUM_9000 8 115 #define TX_FIFO_MAX_NUM 15 116 #define RX_FIFO_MAX_NUM 2 117 #define TX_FIFO_INTERNAL_MAX_NUM 6 118 119 /** 120 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information 121 * 122 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not 123 * accessible) 124 * @shared_mem_size: shared memory size 125 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to 126 * 0x0 as accessible only via DBGM RDAT) 127 * @sample_buff_size: internal sample buff size 128 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre 129 * 8000 HW set to 0x0 as not accessible) 130 * @txfifo_size: size of TXF0 ... TXF7 131 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0 132 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 133 * when paging is not supported this should be 0 134 * @page_buff_size: size of %page_buff_addr 135 * @rxfifo_addr: Start address of rxFifo 136 * @internal_txfifo_addr: start address of internalFifo 137 * @internal_txfifo_size: internal fifos' size 138 * 139 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 140 * set, the last 3 members don't exist. 141 */ 142 struct iwl_shared_mem_cfg_v2 { 143 __le32 shared_mem_addr; 144 __le32 shared_mem_size; 145 __le32 sample_buff_addr; 146 __le32 sample_buff_size; 147 __le32 txfifo_addr; 148 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000]; 149 __le32 rxfifo_size[RX_FIFO_MAX_NUM]; 150 __le32 page_buff_addr; 151 __le32 page_buff_size; 152 __le32 rxfifo_addr; 153 __le32 internal_txfifo_addr; 154 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM]; 155 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */ 156 157 /** 158 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration 159 * 160 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB) 161 * @txfifo_size: size of TX FIFOs 162 * @rxfifo1_addr: RXF1 addr 163 * @rxfifo1_size: RXF1 size 164 */ 165 struct iwl_shared_mem_lmac_cfg { 166 __le32 txfifo_addr; 167 __le32 txfifo_size[TX_FIFO_MAX_NUM]; 168 __le32 rxfifo1_addr; 169 __le32 rxfifo1_size; 170 171 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */ 172 173 /** 174 * struct iwl_shared_mem_cfg - Shared memory configuration information 175 * 176 * @shared_mem_addr: shared memory address 177 * @shared_mem_size: shared memory size 178 * @sample_buff_addr: internal sample (mon/adc) buff addr 179 * @sample_buff_size: internal sample buff size 180 * @rxfifo2_addr: start addr of RXF2 181 * @rxfifo2_size: size of RXF2 182 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 183 * when paging is not supported this should be 0 184 * @page_buff_size: size of %page_buff_addr 185 * @lmac_num: number of LMACs (1 or 2) 186 * @lmac_smem: per - LMAC smem data 187 * @rxfifo2_control_addr: start addr of RXF2C 188 * @rxfifo2_control_size: size of RXF2C 189 */ 190 struct iwl_shared_mem_cfg { 191 __le32 shared_mem_addr; 192 __le32 shared_mem_size; 193 __le32 sample_buff_addr; 194 __le32 sample_buff_size; 195 __le32 rxfifo2_addr; 196 __le32 rxfifo2_size; 197 __le32 page_buff_addr; 198 __le32 page_buff_size; 199 __le32 lmac_num; 200 struct iwl_shared_mem_lmac_cfg lmac_smem[3]; 201 __le32 rxfifo2_control_addr; 202 __le32 rxfifo2_control_size; 203 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */ 204 205 /** 206 * struct iwl_mfuart_load_notif_v1 - mfuart image version & status 207 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 208 * @installed_ver: installed image version 209 * @external_ver: external image version 210 * @status: MFUART loading status 211 * @duration: MFUART loading time 212 */ 213 struct iwl_mfuart_load_notif_v1 { 214 __le32 installed_ver; 215 __le32 external_ver; 216 __le32 status; 217 __le32 duration; 218 } __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */ 219 220 /** 221 * struct iwl_mfuart_load_notif - mfuart image version & status 222 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 223 * @installed_ver: installed image version 224 * @external_ver: external image version 225 * @status: MFUART loading status 226 * @duration: MFUART loading time 227 * @image_size: MFUART image size in bytes 228 */ 229 struct iwl_mfuart_load_notif { 230 __le32 installed_ver; 231 __le32 external_ver; 232 __le32 status; 233 __le32 duration; 234 /* image size valid only in v2 of the command */ 235 __le32 image_size; 236 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */ 237 238 /** 239 * struct iwl_mfu_assert_dump_notif - mfuart dump logs 240 * ( MFU_ASSERT_DUMP_NTF = 0xfe ) 241 * @assert_id: mfuart assert id that cause the notif 242 * @curr_reset_num: number of asserts since uptime 243 * @index_num: current chunk id 244 * @parts_num: total number of chunks 245 * @data_size: number of data bytes sent 246 * @data: data buffer 247 */ 248 struct iwl_mfu_assert_dump_notif { 249 __le32 assert_id; 250 __le32 curr_reset_num; 251 __le16 index_num; 252 __le16 parts_num; 253 __le32 data_size; 254 __le32 data[]; 255 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */ 256 257 /** 258 * enum iwl_mvm_marker_id - marker ids 259 * 260 * The ids for different type of markers to insert into the usniffer logs 261 * 262 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker 263 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime 264 */ 265 enum iwl_mvm_marker_id { 266 MARKER_ID_TX_FRAME_LATENCY = 1, 267 MARKER_ID_SYNC_CLOCK = 2, 268 }; /* MARKER_ID_API_E_VER_2 */ 269 270 /** 271 * struct iwl_mvm_marker - mark info into the usniffer logs 272 * 273 * (MARKER_CMD = 0xcb) 274 * 275 * Mark the UTC time stamp into the usniffer logs together with additional 276 * metadata, so the usniffer output can be parsed. 277 * In the command response the ucode will return the GP2 time. 278 * 279 * @dw_len: The amount of dwords following this byte including this byte. 280 * @marker_id: A unique marker id (iwl_mvm_marker_id). 281 * @reserved: reserved. 282 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC 283 * @metadata: additional meta data that will be written to the unsiffer log 284 */ 285 struct iwl_mvm_marker { 286 u8 dw_len; 287 u8 marker_id; 288 __le16 reserved; 289 __le64 timestamp; 290 __le32 metadata[]; 291 } __packed; /* MARKER_API_S_VER_1 */ 292 293 /** 294 * struct iwl_mvm_marker_rsp - Response to marker cmd 295 * 296 * @gp2: The gp2 clock value in the FW 297 */ 298 struct iwl_mvm_marker_rsp { 299 __le32 gp2; 300 } __packed; 301 302 /* Operation types for the debug mem access */ 303 enum { 304 DEBUG_MEM_OP_READ = 0, 305 DEBUG_MEM_OP_WRITE = 1, 306 DEBUG_MEM_OP_WRITE_BYTES = 2, 307 }; 308 309 #define DEBUG_MEM_MAX_SIZE_DWORDS 32 310 311 /** 312 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory 313 * @op: DEBUG_MEM_OP_* 314 * @addr: address to read/write from/to 315 * @len: in dwords, to read/write 316 * @data: for write opeations, contains the source buffer 317 */ 318 struct iwl_dbg_mem_access_cmd { 319 __le32 op; 320 __le32 addr; 321 __le32 len; 322 __le32 data[]; 323 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */ 324 325 /* Status responses for the debug mem access */ 326 enum { 327 DEBUG_MEM_STATUS_SUCCESS = 0x0, 328 DEBUG_MEM_STATUS_FAILED = 0x1, 329 DEBUG_MEM_STATUS_LOCKED = 0x2, 330 DEBUG_MEM_STATUS_HIDDEN = 0x3, 331 DEBUG_MEM_STATUS_LENGTH = 0x4, 332 }; 333 334 /** 335 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands 336 * @status: DEBUG_MEM_STATUS_* 337 * @len: read dwords (0 for write operations) 338 * @data: contains the read DWs 339 */ 340 struct iwl_dbg_mem_access_rsp { 341 __le32 status; 342 __le32 len; 343 __le32 data[]; 344 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */ 345 346 /** 347 * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command 348 * @operation: suspend or resume operation, uses 349 * &enum iwl_dbg_suspend_resume_cmds 350 */ 351 struct iwl_dbg_suspend_resume_cmd { 352 __le32 operation; 353 } __packed; 354 355 #define BUF_ALLOC_MAX_NUM_FRAGS 16 356 357 /** 358 * struct iwl_buf_alloc_frag - a DBGC fragment 359 * @addr: base address of the fragment 360 * @size: size of the fragment 361 */ 362 struct iwl_buf_alloc_frag { 363 __le64 addr; 364 __le32 size; 365 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */ 366 367 /** 368 * struct iwl_buf_alloc_cmd - buffer allocation command 369 * @alloc_id: &enum iwl_fw_ini_allocation_id 370 * @buf_location: &enum iwl_fw_ini_buffer_location 371 * @num_frags: number of fragments 372 * @frags: fragments array 373 */ 374 struct iwl_buf_alloc_cmd { 375 __le32 alloc_id; 376 __le32 buf_location; 377 __le32 num_frags; 378 struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS]; 379 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */ 380 381 #define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210 382 #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF 383 384 /** 385 * struct iwl_dram_info - DRAM fragments allocation struct 386 * 387 * Driver will fill in the first 1K(+) of the pointed DRAM fragment 388 * 389 * @first_word: magic word value 390 * @second_word: magic word value 391 * @framfrags: DRAM fragmentaion detail 392 */ 393 struct iwl_dram_info { 394 __le32 first_word; 395 __le32 second_word; 396 struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1]; 397 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 398 399 /** 400 * struct iwl_dbgc1_info - DBGC1 address and size 401 * 402 * Driver will fill the dbcg1 address and size at address based on config TLV. 403 * 404 * @first_word: all 0 set as identifier 405 * @dbgc1_add_lsb: LSB bits of DBGC1 physical address 406 * @dbgc1_add_msb: MSB bits of DBGC1 physical address 407 * @dbgc1_size: DBGC1 size 408 */ 409 struct iwl_dbgc1_info { 410 __le32 first_word; 411 __le32 dbgc1_add_lsb; 412 __le32 dbgc1_add_msb; 413 __le32 dbgc1_size; 414 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 415 416 /** 417 * struct iwl_dbg_host_event_cfg_cmd 418 * @enabled_severities: enabled severities 419 */ 420 struct iwl_dbg_host_event_cfg_cmd { 421 __le32 enabled_severities; 422 } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */ 423 424 /** 425 * struct iwl_dbg_dump_complete_cmd - dump complete cmd 426 * 427 * @tp: timepoint whose dump has completed 428 * @tp_data: timepoint data 429 */ 430 struct iwl_dbg_dump_complete_cmd { 431 __le32 tp; 432 __le32 tp_data; 433 } __packed; /* FW_DUMP_COMPLETE_CMD_API_S_VER_1 */ 434 435 #define TAS_LMAC_BAND_HB 0 436 #define TAS_LMAC_BAND_LB 1 437 #define TAS_LMAC_BAND_UHB 2 438 #define TAS_LMAC_BAND_INVALID 3 439 440 /** 441 * struct iwl_mvm_tas_status_per_mac - tas status per lmac 442 * @static_status: tas statically enabled or disabled per lmac - TRUE/FALSE 443 * @static_dis_reason: TAS static disable reason, uses 444 * &enum iwl_mvm_tas_statically_disabled_reason 445 * @dynamic_status: Current TAS status. uses 446 * &enum iwl_mvm_tas_dyna_status 447 * @near_disconnection: is TAS currently near disconnection per lmac? - TRUE/FALSE 448 * @max_reg_pwr_limit: Regulatory power limits in dBm 449 * @sar_limit: SAR limits per lmac in dBm 450 * @band: Band per lmac 451 * @reserved: reserved 452 */ 453 struct iwl_mvm_tas_status_per_mac { 454 u8 static_status; 455 u8 static_dis_reason; 456 u8 dynamic_status; 457 u8 near_disconnection; 458 __le16 max_reg_pwr_limit; 459 __le16 sar_limit; 460 u8 band; 461 u8 reserved[3]; 462 } __packed; /*DEBUG_GET_TAS_STATUS_PER_MAC_S_VER_1*/ 463 464 /** 465 * struct iwl_mvm_tas_status_resp - Response to GET_TAS_STATUS 466 * @tas_fw_version: TAS FW version 467 * @is_uhb_for_usa_enable: is UHB enabled in USA? - TRUE/FALSE 468 * @curr_mcc: current mcc 469 * @block_list: country block list 470 * @tas_status_mac: TAS status per lmac, uses 471 * &struct iwl_mvm_tas_status_per_mac 472 * @in_dual_radio: is TAS in dual radio? - TRUE/FALSE 473 * @reserved: reserved 474 */ 475 struct iwl_mvm_tas_status_resp { 476 u8 tas_fw_version; 477 u8 is_uhb_for_usa_enable; 478 __le16 curr_mcc; 479 __le16 block_list[16]; 480 struct iwl_mvm_tas_status_per_mac tas_status_mac[2]; 481 u8 in_dual_radio; 482 u8 reserved[3]; 483 } __packed; /*DEBUG_GET_TAS_STATUS_RSP_API_S_VER_3*/ 484 485 /** 486 * enum iwl_mvm_tas_dyna_status - TAS current running status 487 * @TAS_DYNA_INACTIVE: TAS status is inactive 488 * @TAS_DYNA_INACTIVE_MVM_MODE: TAS is disabled due because FW is in MVM mode 489 * or is in softap mode. 490 * @TAS_DYNA_INACTIVE_TRIGGER_MODE: TAS is disabled because FW is in 491 * multi user trigger mode 492 * @TAS_DYNA_INACTIVE_BLOCK_LISTED: TAS is disabled because current mcc 493 * is blocklisted mcc 494 * @TAS_DYNA_INACTIVE_UHB_NON_US: TAS is disabled because current band is UHB 495 * and current mcc is USA 496 * @TAS_DYNA_ACTIVE: TAS is currently active 497 * @TAS_DYNA_STATUS_MAX: TAS status max value 498 */ 499 enum iwl_mvm_tas_dyna_status { 500 TAS_DYNA_INACTIVE, 501 TAS_DYNA_INACTIVE_MVM_MODE, 502 TAS_DYNA_INACTIVE_TRIGGER_MODE, 503 TAS_DYNA_INACTIVE_BLOCK_LISTED, 504 TAS_DYNA_INACTIVE_UHB_NON_US, 505 TAS_DYNA_ACTIVE, 506 507 TAS_DYNA_STATUS_MAX, 508 }; /*_TAS_DYNA_STATUS_E*/ 509 510 /** 511 * enum iwl_mvm_tas_statically_disabled_reason - TAS statically disabled reason 512 * @TAS_DISABLED_DUE_TO_BIOS: TAS is disabled because TAS is disabled in BIOS 513 * @TAS_DISABLED_DUE_TO_SAR_6DBM: TAS is disabled because SAR limit is less than 6 Dbm 514 * @TAS_DISABLED_REASON_INVALID: TAS disable reason is invalid 515 * @TAS_DISABLED_REASON_MAX: TAS disable reason max value 516 */ 517 enum iwl_mvm_tas_statically_disabled_reason { 518 TAS_DISABLED_DUE_TO_BIOS, 519 TAS_DISABLED_DUE_TO_SAR_6DBM, 520 TAS_DISABLED_REASON_INVALID, 521 522 TAS_DISABLED_REASON_MAX, 523 }; /*_TAS_STATICALLY_DISABLED_REASON_E*/ 524 525 #endif /* __iwl_fw_api_debug_h__ */ 526