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Searched refs:rlc (Results 1 – 25 of 27) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
100 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
101 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
Damdgpu_ucode.c799 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
800 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; in amdgpu_ucode_init_single_fw()
803 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; in amdgpu_ucode_init_single_fw()
804 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; in amdgpu_ucode_init_single_fw()
807 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; in amdgpu_ucode_init_single_fw()
808 ucode_addr = adev->gfx.rlc.save_restore_list_srm; in amdgpu_ucode_init_single_fw()
811 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
812 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; in amdgpu_ucode_init_single_fw()
815 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
816 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; in amdgpu_ucode_init_single_fw()
[all …]
Dgfx_v7_0.c2485 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
3236 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3237 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3240 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3241 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3245 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3246 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3247 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3249 src_ptr = adev->gfx.rlc.reg_list; in gfx_v7_0_rlc_init()
3250 dws = adev->gfx.rlc.reg_list_size; in gfx_v7_0_rlc_init()
[all …]
Dgfx_v6_0.c2020 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_cp_gfx_start()
2342 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; in gfx_v6_0_rlc_init()
2343 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2346 adev->gfx.rlc.cs_data = si_cs_data; in gfx_v6_0_rlc_init()
2347 src_ptr = adev->gfx.rlc.reg_list; in gfx_v6_0_rlc_init()
2348 dws = adev->gfx.rlc.reg_list_size; in gfx_v6_0_rlc_init()
2349 cs_data = adev->gfx.rlc.cs_data; in gfx_v6_0_rlc_init()
2360 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); in gfx_v6_0_rlc_init()
2361 dws = adev->gfx.rlc.clear_state_size + (256 / 4); in gfx_v6_0_rlc_init()
2366 &adev->gfx.rlc.clear_state_obj, in gfx_v6_0_rlc_init()
[all …]
Dgfx_v8_0.c936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
1055 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1057 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1059 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1061 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1063 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1065 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1067 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1069 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1071 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
[all …]
Dsoc15_common.h41 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
46 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
Dgfx_v11_0.c448 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
621 if (adev->gfx.rlc.cs_data == NULL) in gfx_v11_0_get_csb_buffer()
633 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v11_0_get_csb_buffer()
664 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v11_0_rlc_fini()
665 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v11_0_rlc_fini()
666 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v11_0_rlc_fini()
669 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v11_0_rlc_fini()
670 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v11_0_rlc_fini()
671 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v11_0_rlc_fini()
678 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
[all …]
Dgfx_v9_0.c1090 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1230 !adev->gfx.rlc.is_rlc_v2_1)) in gfx_v9_0_check_if_need_gfxoff()
1444 if (adev->gfx.rlc.cs_data == NULL) in gfx_v9_0_get_csb_buffer()
1456 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v9_0_get_csb_buffer()
1637 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1645 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1653 adev->gfx.rlc.cs_data = gfx9_cs_data; in gfx_v9_0_rlc_init()
1655 cs_data = adev->gfx.rlc.cs_data; in gfx_v9_0_rlc_init()
1666 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v9_0_rlc_init()
2055 if (adev->gfx.rlc.funcs) { in gfx_v9_0_sw_init()
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Dgfx_v10_0.c3887 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
4078 if (adev->gfx.rlc.cs_data == NULL) in gfx_v10_0_get_csb_buffer()
4090 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v10_0_get_csb_buffer()
4121 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v10_0_rlc_fini()
4122 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
4123 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v10_0_rlc_fini()
4126 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v10_0_rlc_fini()
4127 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v10_0_rlc_fini()
4128 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v10_0_rlc_fini()
4135 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v10_0_init_rlcg_reg_access_ctrl()
[all …]
Dgfx_v9_4_3.c361 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_4_3_free_microcode()
809 r = adev->gfx.rlc.funcs->init(adev); in gfx_v9_4_3_sw_init()
893 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); in gfx_v9_4_3_sw_fini()
1038 if (adev->gfx.rlc.is_rlc_v2_1) in gfx_v9_4_3_xcc_init_pg()
1096 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1110 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v9_4_3_rlc_init()
1111 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v9_4_3_rlc_init()
2020 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v9_4_3_hw_init()
2118 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_4_3_soft_reset()
4227 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; in gfx_v9_4_3_set_rlc_funcs()
Damdgpu_ucode.h394 struct rlc_firmware_header_v1_0 rlc; member
Daldebaran.c272 adev->gfx.rlc.funcs->resume(adev); in aldebaran_mode2_restore_ip()
Damdgpu_virt.c990 if (!adev->gfx.rlc.rlcg_reg_access_supported) { in amdgpu_virt_rlcg_reg_rw()
1001 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
Damdgpu_gfx.h350 struct amdgpu_rlc rlc; member
Damdgpu_vm.c653 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid) in amdgpu_vm_flush()
654 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid); in amdgpu_vm_flush()
/linux-6.6.21/drivers/gpu/drm/radeon/
Devergreen.c4117 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4118 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4121 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4122 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4124 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4125 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4129 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4130 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4133 radeon_bo_unpin(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4134 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
[all …]
Dradeon_ucode.h215 struct rlc_firmware_header_v1_0 rlc; member
Dcik.c5806 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc) in cik_update_rlc() argument
5811 if (tmp != rlc) in cik_update_rlc()
5812 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6420 if (rdev->rlc.cp_table_ptr == NULL) in cik_init_cp_pg_table()
6424 dst_ptr = rdev->rlc.cp_table_ptr; in cik_init_cp_pg_table()
6616 if (rdev->rlc.cs_data) { in cik_init_gfx_cgpg()
6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6620 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
6626 if (rdev->rlc.reg_list) { in cik_init_gfx_cgpg()
[all …]
Dsi.c5220 static void si_update_rlc(struct radeon_device *rdev, u32 rlc) in si_update_rlc() argument
5225 if (tmp != rlc) in si_update_rlc()
5226 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5282 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5288 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5688 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5696 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5720 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5732 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5784 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
[all …]
Dni.c2177 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2178 rdev->rlc.reg_list_size = in cayman_startup()
2180 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
/linux-6.6.21/arch/arc/lib/
Dstrcmp.S77 rlc r0,0 ; r0 := r2 > r3 ? 1 : 0
/linux-6.6.21/drivers/net/wireless/intel/iwlwifi/fw/api/
Ddatapath.h457 struct iwl_rlc_properties rlc; member
/linux-6.6.21/drivers/net/wireless/intel/iwlwifi/mvm/
Dphy-ctxt.c181 iwl_mvm_phy_ctxt_set_rxchain(mvm, ctxt, &cmd.rlc.rx_chain_info, in iwl_mvm_phy_send_rlc()
/linux-6.6.21/drivers/media/test-drivers/vicodec/
Dcodec-fwht.c55 rlc(const s16 *in, __be16 *output, int blocktype) in rlc() function
732 size = rlc(cf->coeffs, *rlco, blocktype); in encode_plane()
/linux-6.6.21/drivers/gpu/drm/amd/pm/swsmu/
Damdgpu_smu.c1608 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) in smu_disable_dpms()
1609 adev->gfx.rlc.funcs->stop(adev); in smu_disable_dpms()

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