| /linux-6.6.21/drivers/accel/habanalabs/include/gaudi2/ |
| D | gaudi2_async_ids_map_extended.h | 27 int reset; member
32 { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
34 { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
36 { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
38 { .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
40 { .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
42 { .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
44 { .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
46 { .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
48 { .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
[all …]
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| /linux-6.6.21/Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
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| D | socionext,uniphier-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
19 - socionext,uniphier-sld8-reset
20 - socionext,uniphier-pro5-reset
21 - socionext,uniphier-pxs2-reset
22 - socionext,uniphier-ld6b-reset
23 - socionext,uniphier-ld11-reset
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| D | reset.txt | 3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
[all …]
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| D | socionext,uniphier-glue-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
25 - socionext,uniphier-pxs3-usb3-reset
26 - socionext,uniphier-nx1-usb3-reset
[all …]
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| D | xlnx,zynqmp-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
7 title: Zynq UltraScale+ MPSoC and Versal reset
15 The PS reset subsystem is responsible for handling the external reset
16 input to the device and that all internal reset requirements are met
19 Please also refer to reset.txt in this directory for common reset
20 controller binding usage. Device nodes that need access to reset
21 lines should specify them as a reset phandle in their corresponding
22 node as specified in reset.txt.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
25 <dt-bindings/reset/xlnx-zynqmp-resets.h>
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| D | ti-syscon-reset.txt | 4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
13 and provides reset management functionality for various hardware modules
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
31 Should contain 7 cells for each reset exposed to
33 Cell #1 : offset of the reset assert control
35 Cell #2 : bit position of the reset in the reset
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| D | snps,hsdk-reset.txt | 1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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| D | brcm,brcmstb-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#
7 title: Broadcom STB SW_INIT-style reset controller
10 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
12 reset lines.
14 Please also refer to reset.txt in this directory for common reset
22 const: brcm,brcmstb-reset
27 "#reset-cells":
33 - "#reset-cells"
39 reset: reset-controller@8404318 {
40 compatible = "brcm,brcmstb-reset";
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| D | img,pistachio-reset.txt | 4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
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| D | fsl,imx7-src.yaml | 4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
13 The system reset controller can be used to reset various set of
14 peripherals. Device nodes that need access to reset lines should
15 specify them as a reset phandle in their corresponding node as
16 specified in reset.txt.
18 For list of all valid reset indices see
19 <dt-bindings/reset/imx7-reset.h> for i.MX7,
20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
21 <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
45 '#reset-cells':
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| D | allwinner,sun6i-a31-clock-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml#
20 - allwinner,sun6i-a31-ahb1-reset
21 - allwinner,sun6i-a31-clock-reset
31 "#reset-cells":
34 This additional argument passed to that reset controller is the
35 offset of the bit controlling this particular reset line in the
40 - allwinner,sun6i-a31-ahb1-reset
41 - allwinner,sun6i-a31-clock-reset
47 - "#reset-cells"
55 ahb1_rst: reset@1c202c0 {
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| D | nuvoton,npcm750-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
28 nuvoton,sw-reset-number:
33 Contains the software reset number to restart the SoC.
34 If not specified, software reset is disabled.
39 - '#reset-cells'
46 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
48 compatible = "nuvoton,npcm750-reset";
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| D | snps,axs10x-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml#
7 title: AXS10x reset controller
14 to control reset signals of selected peripherals. For example DW GMAC, etc...
16 represents up-to 32 reset lines.
22 const: snps,axs10x-reset
27 '#reset-cells':
33 - '#reset-cells'
39 reset: reset-controller@11220 {
40 compatible = "snps,axs10x-reset";
41 #reset-cells = <1>;
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| D | qca,ar7100-reset.yaml | 5 $id: http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#
8 title: Qualcomm Atheros AR7xxx/AR9XXX reset controller
17 - qca,ar9132-reset
18 - qca,ar9331-reset
19 - const: qca,ar7100-reset
24 "#reset-cells":
30 - "#reset-cells"
36 reset-controller@1806001c {
37 compatible = "qca,ar9132-reset", "qca,ar7100-reset";
39 #reset-cells = <1>;
|
| /linux-6.6.21/drivers/reset/ |
| D | Makefile | 7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
11 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
12 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
13 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
14 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
15 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
16 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
[all …]
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| D | reset-sunplus.c | 115 struct sp_reset *reset = to_sp_reset(rcdev); in sp_reset_update() local
121 writel(val, reset->base + (index * 4)); in sp_reset_update()
141 struct sp_reset *reset = to_sp_reset(rcdev); in sp_reset_status() local
146 reg = readl(reset->base + (index * 4)); in sp_reset_status()
160 struct sp_reset *reset = container_of(nb, struct sp_reset, notifier); in sp_restart() local
162 sp_reset_assert(&reset->rcdev, 0); in sp_restart()
163 sp_reset_deassert(&reset->rcdev, 0); in sp_restart()
171 struct sp_reset *reset; in sp_reset_probe() local
175 reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); in sp_reset_probe()
176 if (!reset) in sp_reset_probe()
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| D | Kconfig | 11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
22 This option enables support for the external reset functions for
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
43 This enables the reset controller driver for BCM6345 SoCs.
50 This enables the reset controller driver for Marvell Berlin SoCs.
53 tristate "Broadcom STB reset controller"
57 This enables the reset controller driver for Broadcom STB SoCs using
[all …]
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| /linux-6.6.21/drivers/power/reset/ |
| D | at91-reset.c | 118 struct at91_reset *reset = container_of(this, struct at91_reset, nb); in at91_reset() local
141 : "r" (reset->ramc_base[0]), in at91_reset()
142 "r" (reset->ramc_base[1]), in at91_reset()
143 "r" (reset->rstc_base), in at91_reset()
146 "r" (reset->data->reset_args), in at91_reset()
147 "r" (reset->ramc_lpr) in at91_reset()
153 static const char *at91_reset_reason(struct at91_reset *reset) in at91_reset_reason() argument
155 u32 reg = readl(reset->rstc_base + AT91_RSTC_SR); in at91_reset_reason()
195 struct at91_reset *reset = platform_get_drvdata(pdev); in power_on_reason_show() local
197 return sprintf(buf, "%s\n", at91_reset_reason(reset)); in power_on_reason_show()
[all …]
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| /linux-6.6.21/Documentation/driver-api/ |
| D | reset.rst | 10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
21 While some reset controller hardware units also implement system restart
22 functionality, restart handlers are out of scope for the reset controller API.
27 The reset controller API uses these terms with a specific meaning:
[all …]
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| /linux-6.6.21/drivers/clk/visconti/ |
| D | reset.c | 25 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_assert() local
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
40 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_deassert() local
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
46 spin_lock_irqsave(reset->lock, flags); in visconti_reset_deassert()
47 ret = regmap_update_bits(reset->regmap, data->rsoff_offset, rst, rst); in visconti_reset_deassert()
48 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_deassert()
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| /linux-6.6.21/Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
[all …]
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| /linux-6.6.21/arch/arm64/boot/dts/apple/ |
| D | t8103-pmgr.dtsi | 14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
73 #reset-cells = <0>;
82 #reset-cells = <0>;
91 #reset-cells = <0>;
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| D | t8112-pmgr.dtsi | 14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
93 #reset-cells = <0>;
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| /linux-6.6.21/drivers/pmdomain/ti/ |
| D | omap_prm.c | 722 static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id) in _is_valid_reset() argument
724 if (reset->mask & BIT(id)) in _is_valid_reset()
730 static int omap_reset_get_st_bit(struct omap_reset_data *reset, in omap_reset_get_st_bit() argument
733 const struct omap_rst_map *map = reset->prm->data->rstmap; in omap_reset_get_st_bit()
748 struct omap_reset_data *reset = to_omap_reset_data(rcdev); in omap_reset_status() local
750 int st_bit = omap_reset_get_st_bit(reset, id); in omap_reset_status()
751 bool has_rstst = reset->prm->data->rstst || in omap_reset_status()
752 (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); in omap_reset_status()
759 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_status()
767 v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); in omap_reset_status()
[all …]
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