Home
last modified time | relevance | path

Searched refs:regPCIE_CNTL2 (Results 1 – 4 of 4) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dnbio_v7_2.c269 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); in nbio_v7_2_update_medium_grain_light_sleep()
276 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); in nbio_v7_2_update_medium_grain_light_sleep()
292 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); in nbio_v7_2_update_medium_grain_light_sleep()
303 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); in nbio_v7_2_update_medium_grain_light_sleep()
319 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); in nbio_v7_2_get_clockgating_state()
Dnbio_v4_3.c277 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_update_medium_grain_light_sleep()
285 WREG32_SOC15(NBIO, 0, regPCIE_CNTL2, data); in nbio_v4_3_update_medium_grain_light_sleep()
299 data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_get_clockgating_state()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_4_3_0_offset.h6608 #define regPCIE_CNTL2 … macro
Dnbio_7_2_0_offset.h19116 #define regPCIE_CNTL2 … macro