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Searched refs:regCP_ME1_PIPE1_INT_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h481 #define regCP_ME1_PIPE1_INT_CNTL … macro
Dgc_9_4_3_offset.h2942 #define regCP_ME1_PIPE1_INT_CNTL … macro
Dgc_11_0_0_offset.h4234 #define regCP_ME1_PIPE1_INT_CNTL … macro
Dgc_11_0_3_offset.h4454 #define regCP_ME1_PIPE1_INT_CNTL … macro
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_3.c2722 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
Dgfx_v11_0.c5778 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()