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Searched refs:regCP_HQD_PQ_WPTR_POLL_ADDR (Results 1 – 9 of 9) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gc_9_4_3.c343 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR), in kgd_gfx_v9_4_3_hqd_load()
Damdgpu_amdkfd_gfx_v11.c238 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), in hqd_load_v11()
Dmes_v11_0.c856 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in mes_v11_0_queue_init_register()
Dgfx_v9_4_3.c1666 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v9_4_3_xcc_kiq_init_register()
Dgfx_v11_0.c3940 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v11_0_kiq_init_register()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h719 #define regCP_HQD_PQ_WPTR_POLL_ADDR macro
Dgc_9_4_3_offset.h3308 #define regCP_HQD_PQ_WPTR_POLL_ADDR macro
Dgc_11_0_0_offset.h4626 #define regCP_HQD_PQ_WPTR_POLL_ADDR macro
Dgc_11_0_3_offset.h4850 #define regCP_HQD_PQ_WPTR_POLL_ADDR macro