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Searched refs:regCP_HQD_PQ_WPTR_HI (Results 1 – 9 of 9) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v11.c198 reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v11()
236 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI), in hqd_load_v11()
333 reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++) in hqd_dump_v11()
Damdgpu_amdkfd_gc_9_4_3.c341 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_4_3_hqd_load()
Dmes_v11_0.c1133 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); in mes_v11_0_kiq_dequeue()
Dgfx_v9_4_3.c1635 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
1693 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
1746 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); in gfx_v9_4_3_xcc_q_fini_register()
Dgfx_v11_0.c3909 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
3959 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h807 #define regCP_HQD_PQ_WPTR_HI … macro
Dgc_9_4_3_offset.h3396 #define regCP_HQD_PQ_WPTR_HI … macro
Dgc_11_0_0_offset.h4714 #define regCP_HQD_PQ_WPTR_HI … macro
Dgc_11_0_3_offset.h4938 #define regCP_HQD_PQ_WPTR_HI … macro