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Searched refs:rFPGA0_XA_RFInterfaceOE (Results 1 – 8 of 8) sorted by relevance

/linux-6.6.21/drivers/staging/rtl8192u/
Dr819xU_phyreg.h24 #define rFPGA0_XA_RFInterfaceOE 0x860 macro
Dr819xU_phy.c569 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; in rtl8192_InitBBRFRegDef()
579 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; in rtl8192_InitBBRFRegDef()
/linux-6.6.21/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c307 priv->phy_reg_def[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; in _rtl92e_init_bb_rf_reg_def()
310 priv->phy_reg_def[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; in _rtl92e_init_bb_rf_reg_def()
979 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); in rtl92e_set_rf_off()
1029 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, in _rtl92e_set_rf_power_state()
Dr8192E_phyreg.h56 #define rFPGA0_XA_RFInterfaceOE 0x860 macro
/linux-6.6.21/drivers/staging/rtl8723bs/hal/
Drtl8723b_phycfg.c315 …pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from … in phy_InitBBRFRegisterDefinition()
319 …pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from … in phy_InitBBRFRegisterDefinition()
DHalPhyRf_8723B.c1362 rFPGA0_XA_RFInterfaceOE, in phy_IQCalibrate_8723B()
/linux-6.6.21/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h111 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ macro
/linux-6.6.21/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h122 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ macro