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Searched refs:postdiv1 (Results 1 – 10 of 10) sorted by relevance

/linux-6.6.21/drivers/clk/starfive/ !
Dclk-starfive-jh7110-pll.c85 unsigned postdiv1 : 2; member
151 u32 postdiv1; member
165 .postdiv1 = 0,
171 .postdiv1 = 0,
177 .postdiv1 = 0,
183 .postdiv1 = 0,
189 .postdiv1 = 0,
195 .postdiv1 = 0,
201 .postdiv1 = 0,
207 .postdiv1 = 0,
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/linux-6.6.21/drivers/clk/pistachio/ !
Dclk-pll.c240 (params->postdiv1 != old_postdiv1 || in pll_gf40lp_frac_set_rate()
244 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_frac_set_rate()
253 (params->postdiv1 << PLL_FRAC_CTRL2_POSTDIV1_SHIFT) | in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
280 postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) & in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
386 (params->postdiv1 != old_postdiv1 || in pll_gf40lp_laint_set_rate()
390 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_laint_set_rate()
399 (params->postdiv1 << PLL_INT_CTRL1_POSTDIV1_SHIFT) | in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
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Dclk.h99 unsigned long long postdiv1; member
/linux-6.6.21/drivers/clk/rockchip/ !
Dclk-pll.c147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) in rockchip_rk3036_pll_get_params()
183 do_div(rate64, cur.postdiv1); in rockchip_rk3036_pll_recalc_rate()
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
324 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
631 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) in rockchip_rk3399_pll_get_params()
665 do_div(rate64, cur.postdiv1); in rockchip_rk3399_pll_recalc_rate()
683 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
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Dclk.h297 .postdiv1 = _postdiv1, \
360 unsigned int postdiv1; member
/linux-6.6.21/drivers/clk/visconti/ !
Dpll.h33 .postdiv1 = _postdiv1, \
44 unsigned int postdiv1; member
Dpll.c49 #define PLL_CREATE_OSTDIV(table) (table->postdiv2 << 4 | table->postdiv1)
71 rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK; in visconti_pll_get_params()
/linux-6.6.21/drivers/gpu/drm/msm/dsi/phy/ !
Ddsi_phy_28nm_8960.c52 u8 postdiv1; member
353 cached_state->postdiv1 = in dsi_28nm_pll_save_state()
379 cached_state->postdiv1); in dsi_28nm_pll_restore_state()
Ddsi_phy_28nm.c65 u8 postdiv1; member
564 cached_state->postdiv1 = in dsi_28nm_pll_save_state()
591 cached_state->postdiv1); in dsi_28nm_pll_restore_state()
/linux-6.6.21/drivers/clk/ !
Dclk-bm1880.c478 u32 postdiv1, postdiv2, denominator; in bm1880_pll_rate_calc() local
482 postdiv1 = (regval >> 8) & 0x7; in bm1880_pll_rate_calc()
486 denominator = refdiv * postdiv1 * postdiv2; in bm1880_pll_rate_calc()