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Searched refs:post_div_table (Results 1 – 25 of 43) sorted by relevance

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/linux-6.6.21/drivers/clk/qcom/
Dclk-alpha-pll.c1424 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1425 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1446 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1447 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1461 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1475 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1476 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1498 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1521 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1522 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
[all …]
Dcamcc-sc7280.c85 .post_div_table = post_div_table_cam_cc_pll0_out_even,
108 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
160 .post_div_table = post_div_table_cam_cc_pll1_out_even,
210 .post_div_table = post_div_table_cam_cc_pll2_out_aux,
233 .post_div_table = post_div_table_cam_cc_pll2_out_aux2,
285 .post_div_table = post_div_table_cam_cc_pll3_out_even,
337 .post_div_table = post_div_table_cam_cc_pll4_out_even,
389 .post_div_table = post_div_table_cam_cc_pll5_out_even,
441 .post_div_table = post_div_table_cam_cc_pll6_out_even,
464 .post_div_table = post_div_table_cam_cc_pll6_out_odd,
Dgpucc-sm6115.c90 .post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
145 .post_div_table = post_div_table_gpu_cc_pll1_out_aux,
Dlpassaudiocc-sc7280.c105 .post_div_table = post_div_table_lpass_audio_cc_pll_out_aux2,
160 .post_div_table = post_div_table_lpass_aon_cc_pll_out_even,
182 .post_div_table = post_div_table_lpass_aon_cc_pll_out_odd,
Dcamcc-sm8450.c92 .post_div_table = post_div_table_cam_cc_pll0_out_even,
115 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
163 .post_div_table = post_div_table_cam_cc_pll1_out_even,
234 .post_div_table = post_div_table_cam_cc_pll3_out_even,
282 .post_div_table = post_div_table_cam_cc_pll4_out_even,
330 .post_div_table = post_div_table_cam_cc_pll5_out_even,
378 .post_div_table = post_div_table_cam_cc_pll6_out_even,
426 .post_div_table = post_div_table_cam_cc_pll7_out_even,
474 .post_div_table = post_div_table_cam_cc_pll8_out_even,
Dclk-alpha-pll.h111 const struct clk_div_table *post_div_table; member
Dgcc-sm6115.c84 .post_div_table = post_div_table_gpll0_out_aux2,
104 .post_div_table = post_div_table_gpll0_out_main,
154 .post_div_table = post_div_table_gpll10_out_main,
208 .post_div_table = post_div_table_gpll11_out_main,
267 .post_div_table = post_div_table_gpll4_out_main,
306 .post_div_table = post_div_table_gpll6_out_main,
345 .post_div_table = post_div_table_gpll7_out_main,
402 .post_div_table = post_div_table_gpll8_out_main,
454 .post_div_table = post_div_table_gpll9_out_main,
Dmmcc-msm8998.c76 .post_div_table = post_div_table_fabia_even,
108 .post_div_table = post_div_table_fabia_even,
136 .post_div_table = post_div_table_fabia_even,
164 .post_div_table = post_div_table_fabia_even,
192 .post_div_table = post_div_table_fabia_even,
220 .post_div_table = post_div_table_fabia_even,
248 .post_div_table = post_div_table_fabia_even,
276 .post_div_table = post_div_table_fabia_even,
Dcamcc-sm8250.c79 .post_div_table = post_div_table_cam_cc_pll0_out_even,
102 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
153 .post_div_table = post_div_table_cam_cc_pll1_out_even,
204 .post_div_table = post_div_table_cam_cc_pll2_out_main,
255 .post_div_table = post_div_table_cam_cc_pll3_out_even,
306 .post_div_table = post_div_table_cam_cc_pll4_out_even,
Dcamcc-sdm845.c52 .post_div_table = post_div_table_fabia_even,
84 .post_div_table = post_div_table_fabia_even,
116 .post_div_table = post_div_table_fabia_even,
148 .post_div_table = post_div_table_fabia_even,
Dgpucc-msm8998.c80 .post_div_table = post_div_table_fabia_even,
Dlpasscorecc-sc7280.c73 .post_div_table = post_div_table_lpass_core_cc_dig_pll_out_odd,
Dlpasscorecc-sc7180.c89 .post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
Dgcc-qcm2290.c82 .post_div_table = post_div_table_gpll0_out_aux2,
199 .post_div_table = post_div_table_gpll3_out_main,
270 .post_div_table = post_div_table_gpll6_out_main,
343 .post_div_table = post_div_table_gpll8_out_main,
395 .post_div_table = post_div_table_gpll9_out_main,
Dgcc-sm6375.c86 .post_div_table = post_div_table_gpll0_out_even,
108 .post_div_table = post_div_table_gpll0_out_odd,
228 .post_div_table = post_div_table_gpll3_out_even,
301 .post_div_table = post_div_table_gpll6_out_even,
372 .post_div_table = post_div_table_gpll8_out_even,
424 .post_div_table = post_div_table_gpll9_out_main,
Dcamcc-sm6350.c76 .post_div_table = post_div_table_camcc_pll0_out_even,
128 .post_div_table = post_div_table_camcc_pll1_out_even,
194 .post_div_table = post_div_table_camcc_pll2_out_main,
Ddispcc-sm6115.c81 .post_div_table = post_div_table_disp_cc_pll0_out_main,
Dgcc-qdu1000.c74 .post_div_table = post_div_table_gcc_gpll0_out_even,
108 .post_div_table = post_div_table_gcc_gpll0_out_even,
142 .post_div_table = post_div_table_gcc_gpll0_out_even,
210 .post_div_table = post_div_table_gcc_gpll0_out_even,
Ddispcc-sc7180.c60 .post_div_table = post_div_table_disp_cc_pll0_out_even,
/linux-6.6.21/drivers/clk/imx/
Dclk-imx6sl.c80 static const struct clk_div_table post_div_table[] = { variable
267 …v", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
269 …v", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
Dclk-imx6sll.c59 static const struct clk_div_table post_div_table[] = { variable
176 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
180 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
Dclk-imx6q.c104 static struct clk_div_table post_div_table[] = { variable
467 post_div_table[1].div = 1; in imx6q_clocks_init()
468 post_div_table[2].div = 1; in imx6q_clocks_init()
598 …post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
603 …post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
Dclk-imx6ul.c83 static const struct clk_div_table post_div_table[] = { variable
233 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
237 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
Dclk-imx6sx.c96 static const struct clk_div_table post_div_table[] = { variable
248 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
252 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
Dclk-imx7d.c36 static const struct clk_div_table post_div_table[] = { variable
434 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
438 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()

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