Home
last modified time | relevance | path

Searched refs:pll_state (Results 1 – 8 of 8) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/i915/display/
Dintel_cx0_phy.c1766 struct intel_cx0pll_state *pll_state = &crtc_state->cx0pll_state; in intel_c10pll_update_pll() local
1773 pll_state->ssc_enabled = in intel_c10pll_update_pll()
1778 if (pll_state->ssc_enabled) in intel_c10pll_update_pll()
1781 drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); in intel_c10pll_update_pll()
1783 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
1809 struct intel_c10pll_state *pll_state) in intel_c10pll_readout_hw_state() argument
1826 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
1827 pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane, in intel_c10pll_readout_hw_state()
1830 pll_state->cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
1831 pll_state->tx = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
[all …]
Dintel_cx0_phy.h29 …intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c10pll_state *pll_state);
34 const struct intel_c10pll_state *pll_state);
38 struct intel_c20pll_state *pll_state);
42 const struct intel_c20pll_state *pll_state);
Dintel_dpll_mgr.c92 const struct intel_dpll_hw_state *pll_state);
310 const struct intel_dpll_hw_state *pll_state, in intel_find_shared_dpll() argument
332 if (memcmp(pll_state, in intel_find_shared_dpll()
334 sizeof(*pll_state)) == 0) { in intel_find_shared_dpll()
383 const struct intel_dpll_hw_state *pll_state) in intel_reference_shared_dpll() argument
391 shared_dpll[id].hw_state = *pll_state; in intel_reference_shared_dpll()
923 const struct intel_dpll_hw_state *pll_state) in hsw_ddi_wrpll_get_freq() argument
927 u32 wrpll = pll_state->wrpll; in hsw_ddi_wrpll_get_freq()
1047 const struct intel_dpll_hw_state *pll_state) in hsw_ddi_lcpll_get_freq() argument
1098 const struct intel_dpll_hw_state *pll_state) in hsw_ddi_spll_get_freq() argument
[all …]
Dintel_snps_phy.c1824 const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state; in intel_mpllb_enable() local
1833 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); in intel_mpllb_enable()
1834 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); in intel_mpllb_enable()
1835 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); in intel_mpllb_enable()
1836 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); in intel_mpllb_enable()
1837 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); in intel_mpllb_enable()
1838 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); in intel_mpllb_enable()
1839 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); in intel_mpllb_enable()
1860 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); in intel_mpllb_enable()
1920 const struct intel_mpllb_state *pll_state) in intel_mpllb_calc_port_clock() argument
[all …]
Dintel_snps_phy.h28 struct intel_mpllb_state *pll_state);
30 const struct intel_mpllb_state *pll_state);
Dintel_dpll_mgr.h347 const struct intel_dpll_hw_state *pll_state);
/linux-6.6.21/drivers/clk/
Dclk-stm32f4.c667 int pll_state; in stm32f4_pll_set_rate() local
669 pll_state = stm32f4_pll_is_enabled(hw); in stm32f4_pll_set_rate()
671 if (pll_state) in stm32f4_pll_set_rate()
680 if (pll_state) in stm32f4_pll_set_rate()
717 int pll_state, ret; in stm32f4_pll_div_set_rate() local
722 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
724 if (pll_state) in stm32f4_pll_div_set_rate()
729 if (pll_state) in stm32f4_pll_div_set_rate()
/linux-6.6.21/sound/soc/codecs/
Dwm8580.c228 struct pll_state { struct
248 struct pll_state a; argument
249 struct pll_state b;
466 struct pll_state *state; in wm8580_set_dai_pll()