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Searched refs:plane_res (Results 1 – 25 of 33) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c151 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in dce60_set_default_colors()
158 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in dce60_set_default_colors()
160 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( in dce60_set_default_colors()
161 pipe_ctx->plane_res.xfm, &default_adjust); in dce60_set_default_colors()
202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color()
246 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dce60_program_scaler()
247 pipe_ctx->plane_res.xfm, in dce60_program_scaler()
248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler()
265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c801 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport_size()
999 if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp) in adjust_recout_for_visual_confirm()
1003 dpp_offset *= pipe_ctx->plane_res.dpp->inst; in adjust_recout_for_visual_confirm()
1162 pipe_ctx->plane_res.scl_data.recout = shift_rec( in calculate_recout()
1166 &pipe_ctx->plane_res.scl_data.recout, in calculate_recout()
1170 memset(&pipe_ctx->plane_res.scl_data.recout, 0, in calculate_recout()
1191 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1194 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1199 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
1201 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
[all …]
Ddc_stream.c413 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
415 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position()
416 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position()
705 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
Ddc_hw_sequencer.c333 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
390 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
568 …ce[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; in hwss_build_fast_sequence()
727 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_setup_dpp()
744 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_program_bias_and_scale()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c281 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
609 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
1378 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) in program_scaler()
1388 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in program_scaler()
1389 pipe_ctx->plane_res.xfm, in program_scaler()
1390 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1407 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
1408 &pipe_ctx->plane_res.scl_data); in program_scaler()
1590 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in apply_single_controller_ctx_to_hw()
1850 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_displaymarks()
[all …]
Ddce110_resource.c1138 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1140 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; in dce110_acquire_underlay()
1174 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, in dce110_acquire_underlay()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) in dcn20_set_flip_control_gsl()
183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( in dcn20_set_flip_control_gsl()
184 pipe_ctx->plane_res.hubp, flip_immediate); in dcn20_set_flip_control_gsl()
278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_triple_buffer()
280 pipe_ctx->plane_res.hubp, in dcn20_program_triple_buffer()
586 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn20_plane_atomic_disable()
587 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable()
609 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable()
610 pipe_ctx->plane_res.hubp); in dcn20_plane_atomic_disable()
[all …]
Ddcn20_resource.c1474 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1475 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1476 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1477 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1478 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1479 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1497 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1514 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1559 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1560 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calcs.c318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c538 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur()
1086 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1111 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1124 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1134 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1146 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1184 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disconnect()
1185 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect()
1202 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1261 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disable()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_hwseq.c146 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( in dcn201_update_plane_addr()
147 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr()
310 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw()
311 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
312 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
320 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw()
343 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw()
375 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect()
376 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
407 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_plane_atomic_disconnect()
[all …]
Ddcn201_resource.c1015 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1016 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1017 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1018 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_free_pipe_for_layer()
/linux-6.6.21/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_trace.h386 const struct plane_resource *plane_res,
388 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
439 __entry->recout_x = plane_res->scl_data.recout.x;
440 __entry->recout_y = plane_res->scl_data.recout.y;
441 __entry->recout_w = plane_res->scl_data.recout.width;
442 __entry->recout_h = plane_res->scl_data.recout.height;
443 __entry->viewport_x = plane_res->scl_data.viewport.x;
444 __entry->viewport_y = plane_res->scl_data.viewport.y;
445 __entry->viewport_w = plane_res->scl_data.viewport.width;
446 __entry->viewport_h = plane_res->scl_data.viewport.height;
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/
Ddc_dmub_srv.c307 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
312 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
691 …>pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info()
693 …ipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info()
845 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; in dc_can_pipe_disable_cursor()
861 r2 = test_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor()
873 r2_half = split_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor()
912 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dc_build_cursor_update_payload0()
1006 pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
1016 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
Ddc_trace.h31 pipe_ctx->stream, &pipe_ctx->plane_res, \
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_resource_helpers.c61 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
148 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
162 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
Ddcn32_hwseq.c442 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut()
443 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut()
478 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mcm_luts()
479 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mcm_luts()
526 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_input_transfer_func()
566 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_output_transfer_func()
608 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_force_pstate()
629 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_force_pstate()
660 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_mall_sel()
720 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_program_mall_pipe_config()
Ddcn32_resource.c2664 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2665 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2666 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2667 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2696 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2697 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2698 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2699 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c75 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
96 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
97 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
151 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
193 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func()
400 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
663 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn30_program_dmdata_engine()
Ddcn30_resource.c1534 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1535 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1536 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1537 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1538 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1539 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1742 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
1757 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c172 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
173 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce/
Ddmub_replay.c174 if (pipe_ctx->plane_res.dpp) in dmub_replay_copy_settings()
175 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_replay_copy_settings()
Ddmub_psr.c343 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
345 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
346 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
Ddcn32_clk_mgr.c302 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn32_update_clocks_update_dpp_dto()
304 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) in dcn32_update_clocks_update_dpp_dto()
305 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn32_update_clocks_update_dpp_dto()
306 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { in dcn32_update_clocks_update_dpp_dto()
311 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { in dcn32_update_clocks_update_dpp_dto()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c1428 … context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn32_calculate_dlg_params()
1430 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; in dcn32_calculate_dlg_params()
1588 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1589 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1590 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1591 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1592 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1593 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn32_split_stream_for_mpc_or_odm()
1783 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_internal_validate_bw()
1799 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_internal_validate_bw()

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