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Searched refs:phy_write (Results 1 – 25 of 82) sorted by relevance

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/linux-6.6.21/drivers/net/phy/
Dvitesse.c99 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
108 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
134 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
136 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
150 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
152 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
153 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
156 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
157 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
159 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
[all …]
Dnational.c54 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
60 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
61 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
73 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
92 phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7); in ns_handle_interrupt()
108 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
111 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
128 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
129 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
[all …]
Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
Ddavicom.c87 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
90 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
159 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
164 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
Dmeson-gxl.c48 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
51 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
54 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
57 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
62 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
74 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
98 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
102 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
42 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
260 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
316 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
317 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
358 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
362 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */ in lan88xx_link_change_notify()
364 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */ in lan88xx_link_change_notify()
[all …]
Dbcm7xxx.c79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
265 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
270 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
280 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
336 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
340 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
346 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
350 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
355 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
[all …]
Ddp83tc811.c217 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
232 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
244 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
255 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
316 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
321 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
337 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
340 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
[all …]
Dbcm63xx.c34 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
37 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
60 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
69 return phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
Dcicada.c67 err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT, in cis820x_config_init()
73 err = phy_write(phydev, MII_CIS8201_EXT_CON1, in cis820x_config_init()
95 err = phy_write(phydev, MII_CIS8201_IMASK, in cis820x_config_intr()
98 err = phy_write(phydev, MII_CIS8201_IMASK, 0); in cis820x_config_intr()
Dlxt.c88 err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); in lxt970_config_intr()
90 err = phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
129 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
152 err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); in lxt971_config_intr()
154 err = phy_write(phydev, MII_LXT971_IER, 0); in lxt971_config_intr()
292 phy_write(phydev, MII_BMCR, val); in lxt973_probe()
Ddp83869.c209 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
211 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
337 return phy_write(phydev, MII_DP83869_MICR, val_micr); in dp83869_set_wol()
622 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); in dp83869_configure_rgmii()
711 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); in dp83869_configure_mode()
721 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
726 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); in dp83869_configure_mode()
748 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
759 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
765 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
[all …]
Dqsemi.c71 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); in qs6612_config_init()
110 err = phy_write(phydev, MII_QS6612_IMR, in qs6612_config_intr()
113 err = phy_write(phydev, MII_QS6612_IMR, 0); in qs6612_config_intr()
Dste10Xp.c40 err = phy_write(phydev, MII_BMCR, value); in ste10Xp_config_init()
72 err = phy_write(phydev, MII_XIE, MII_XIE_DEFAULT_MASK); in ste10Xp_config_intr()
74 err = phy_write(phydev, MII_XIE, 0); in ste10Xp_config_intr()
Dbcm-phy-lib.c111 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK | in bcm54xx_auxctl_read()
119 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
129 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
136 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
153 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
160 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
198 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
201 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
244 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow)); in bcm_phy_read_shadow()
252 return phy_write(phydev, MII_BCM54XX_SHD, in bcm_phy_write_shadow()
[all …]
Dbcm-cygnus.c25 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
55 rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02); in bcm_cygnus_afe_config()
85 rc = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_cygnus_config_init()
93 rc = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm_cygnus_config_init()
Ddp83848.c77 ret = phy_write(phydev, DP83848_MISR, DP83848_INT_EN_MASK); in dp83848_config_intr()
81 ret = phy_write(phydev, DP83848_MICR, control); in dp83848_config_intr()
84 ret = phy_write(phydev, DP83848_MICR, control); in dp83848_config_intr()
Dbroadcom.c98 phy_write(phydev, MII_CTRL1000, val); in bcm54210e_config_init()
360 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init()
368 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init()
500 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN); in bcm54xx_suspend()
683 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in brcm_fet_config_init()
718 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_init()
729 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); in brcm_fet_config_init()
743 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); in brcm_fet_config_init()
761 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); in brcm_fet_config_init()
794 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()
[all …]
Drealtek.c197 err = phy_write(phydev, RTL821x_INER, in rtl8211b_config_intr()
200 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211b_config_intr()
219 err = phy_write(phydev, RTL821x_INER, in rtl8211e_config_intr()
222 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211e_config_intr()
328 phy_write(phydev, 0x17, 0x2138); in rtl8211_config_aneg()
329 phy_write(phydev, 0x0e, 0x0260); in rtl8211_config_aneg()
331 phy_write(phydev, 0x17, 0x2108); in rtl8211_config_aneg()
332 phy_write(phydev, 0x0e, 0x0000); in rtl8211_config_aneg()
515 phy_write(phydev, MII_MMD_DATA, BIT(9)); in rtl8211b_suspend()
522 phy_write(phydev, MII_MMD_DATA, 0); in rtl8211b_resume()
[all …]
/linux-6.6.21/drivers/net/ethernet/realtek/
Dr8169_phy_config.c285 phy_write(phydev, 0x1f, 0x0001); in rtl8168bb_hw_phy_config()
287 phy_write(phydev, 0x10, 0xf41b); in rtl8168bb_hw_phy_config()
288 phy_write(phydev, 0x1f, 0x0000); in rtl8168bb_hw_phy_config()
300 phy_write(phydev, 0x1d, 0x0f00); in rtl8168cp_1_hw_phy_config()
438 phy_write(phydev, 0x1f, 0x0005); in rtl8168d_apply_firmware_cond()
439 phy_write(phydev, 0x05, 0x001b); in rtl8168d_apply_firmware_cond()
441 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_apply_firmware_cond()
455 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_common()
468 phy_write(phydev, 0x0d, val | set[i]); in rtl8168d_1_common()
481 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
[all …]
/linux-6.6.21/drivers/net/ethernet/ibm/emac/
Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/linux-6.6.21/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c142 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
324 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
325 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
326 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
327 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
328 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
329 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
330 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
346 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
347 phy_write(phy, CN(priv->cfg.cn), DPHY_CN); in mixel_dphy_set_pll_params()
[all …]
/linux-6.6.21/arch/powerpc/platforms/85xx/
Dmpc85xx_mds.c67 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); in mpc8568_fixup_125_clock()
72 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in mpc8568_fixup_125_clock()
82 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); in mpc8568_fixup_125_clock()
93 err = phy_write(phydev,29, 0x0006); in mpc8568_mds_phy_fixups()
104 err = phy_write(phydev,30, temp); in mpc8568_mds_phy_fixups()
109 err = phy_write(phydev,29, 0x000a); in mpc8568_mds_phy_fixups()
126 err = phy_write(phydev,30,temp); in mpc8568_mds_phy_fixups()
138 err = phy_write(phydev,16,temp); in mpc8568_mds_phy_fixups()
/linux-6.6.21/arch/arm/mach-imx/
Dmach-imx7d.c20 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
21 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
22 phy_write(dev, 0x1e, 0x2f); in bcm54220_phy_fixup()
23 phy_write(dev, 0x1f, 0x71b7); in bcm54220_phy_fixup()
Dmach-imx6q.c28 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
33 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
36 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()

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