Home
last modified time | relevance | path

Searched refs:phy_clear_bits_mmd (Results 1 – 17 of 17) sorted by relevance

/linux-6.6.21/drivers/net/phy/
Dmediatek-ge-soc.c342 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
552 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw()
559 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
562 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
570 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
573 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
581 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
584 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
592 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
595 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
[all …]
Dadin1100.c105 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL, in adin_config_aneg()
114 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
129 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
172 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, in adin_set_loopback()
Dnxp-c45-tja11xx.c659 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S, in tja1120_get_hwtxts()
827 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
847 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
856 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
1225 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1251 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1356 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_get_status()
1358 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_get_status()
1385 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1445 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE); in nxp_c45_disable_delays()
[all …]
Dmediatek-ge.c62 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); in mt7531_phy_config_init()
Ddp83822.c177 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
329 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, in dp8382x_disable_wol()
415 phy_clear_bits_mmd(phydev, DP83822_DEVADDR, in dp83822_config_init()
Ddp83tc811.c151 return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
350 return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, in dp83811_config_init()
Dphy-c45.c56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
325 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
1167 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1262 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
Ddp83td510.c78 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
Dmarvell-88x2222.c65 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, in mv2222_tx_enable()
92 int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, in mv2222_disable_aneg()
Dmarvell10g.c328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
392 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, in mv3310_set_downshift()
637 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
1336 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
Dadin.c260 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode()
306 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
Ddp83867.c486 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_port_mirroring()
760 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_init()
Dmicrel.c4136 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin)); in lan8841_ptp_perout_off()
4140 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin)); in lan8841_ptp_perout_off()
4144 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin)); in lan8841_ptp_perout_off()
4189 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp); in lan8841_ptp_remove_event()
4192 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp); in lan8841_ptp_remove_event()
4204 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp); in lan8841_ptp_remove_event()
4402 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin)); in lan8841_ptp_extts_on()
4427 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin)); in lan8841_ptp_extts_off()
4431 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin)); in lan8841_ptp_extts_off()
Daquantia_main.c706 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_resume()
Ddp83869.c504 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, in dp83869_config_port_mirroring()
Dmxl-gpy.c722 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
/linux-6.6.21/include/linux/
Dphy.h1494 static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad, in phy_clear_bits_mmd() function