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Searched refs:phase (Results 1 – 25 of 457) sorted by relevance

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/linux-6.6.21/drivers/clk/hisilicon/
Dclk-hisi-phase.c30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
58 for (i = 0; i < phase->phase_num; i++) in hisi_phase_degrees_to_regval()
[all …]
/linux-6.6.21/drivers/clk/sunxi-ng/
Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
/linux-6.6.21/drivers/gpu/drm/tidss/
Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
/linux-6.6.21/drivers/clk/sunxi/
Dclk-mod0.c173 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
179 value = readl(phase->reg); in mmc_get_phase()
180 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
215 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
266 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
267 value = readl(phase->reg); in mmc_set_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
269 value |= delay << phase->offset; in mmc_set_phase()
270 writel(value, phase->reg); in mmc_set_phase()
271 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
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/linux-6.6.21/drivers/hwmon/pmbus/
Dmp2888.c94 mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, int phase, u8 reg) in mp2888_read_phase() argument
98 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_phase()
102 if (!((phase + 1) % 2)) in mp2888_read_phase()
128 mp2888_read_phases(struct i2c_client *client, struct mp2888_data *data, int page, int phase) in mp2888_read_phases() argument
132 switch (phase) { in mp2888_read_phases()
134 ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS1_2); in mp2888_read_phases()
137 ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS3_4); in mp2888_read_phases()
140 ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS5_6); in mp2888_read_phases()
143 ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS7_8); in mp2888_read_phases()
146 ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS9_10); in mp2888_read_phases()
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Dmp2975.c130 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
133 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
197 int page, int phase, u8 reg) in mp2975_read_phase() argument
201 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
205 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
228 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
238 int page, int phase) in mp2975_read_phases() argument
243 switch (phase) { in mp2975_read_phases()
245 ret = mp2975_read_phase(client, data, page, phase, in mp2975_read_phases()
249 ret = mp2975_read_phase(client, data, page, phase, in mp2975_read_phases()
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Dir35221.c25 int phase, int reg) in ir35221_read_word_data() argument
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
Dlt7182s.c35 static int lt7182s_read_word_data(struct i2c_client *client, int page, int phase, int reg) in lt7182s_read_word_data() argument
42 ret = pmbus_read_word_data(client, page, phase, MFR_READ_ITH); in lt7182s_read_word_data()
44 ret = pmbus_read_word_data(client, 0, phase, MFR_READ_EXTVCC); in lt7182s_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, MFR_IOUT_PEAK); in lt7182s_read_word_data()
50 ret = pmbus_read_word_data(client, page, phase, MFR_VOUT_PEAK); in lt7182s_read_word_data()
53 ret = pmbus_read_word_data(client, page, phase, MFR_VIN_PEAK); in lt7182s_read_word_data()
56 ret = pmbus_read_word_data(client, page, phase, MFR_TEMPERATURE_1_PEAK); in lt7182s_read_word_data()
Dltc3815.c73 int phase, int reg) in ltc3815_read_word_data() argument
79 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
83 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
87 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
91 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
95 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
/linux-6.6.21/drivers/char/
Dppdev.c397 pp->saved_state.phase = info->phase; in pp_do_ioctl()
399 info->phase = pp->state.phase; in pp_do_ioctl()
428 pp->state.phase = init_phase(mode); in pp_do_ioctl()
432 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
452 int phase; in pp_do_ioctl() local
454 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
458 pp->state.phase = phase; in pp_do_ioctl()
461 pp->pdev->port->ieee1284.phase = phase; in pp_do_ioctl()
467 int phase; in pp_do_ioctl() local
470 phase = pp->pdev->port->ieee1284.phase; in pp_do_ioctl()
[all …]
/linux-6.6.21/drivers/gpu/drm/imx/dcss/
Ddcss-scaler.c178 int phase; in dcss_scaler_gaussian_filter() local
183 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
184 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
185 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
232 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
237 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
239 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
243 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
589 int i, phase; in dcss_scaler_program_5_coef_set() local
605 for (phase = (PSC_NUM_PHASES >> 1) - 1; in dcss_scaler_program_5_coef_set()
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/linux-6.6.21/lib/zstd/compress/
Dzstd_cwksp.h153 ZSTD_cwksp_alloc_phase_e phase; member
273 ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_internal_advance_phase() argument
275 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
276 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
278 if (ws->phase < ZSTD_cwksp_alloc_buffers && in ZSTD_cwksp_internal_advance_phase()
279 phase >= ZSTD_cwksp_alloc_buffers) { in ZSTD_cwksp_internal_advance_phase()
284 if (ws->phase < ZSTD_cwksp_alloc_aligned && in ZSTD_cwksp_internal_advance_phase()
285 phase >= ZSTD_cwksp_alloc_aligned) { in ZSTD_cwksp_internal_advance_phase()
306 ws->phase = phase; in ZSTD_cwksp_internal_advance_phase()
324 ZSTD_cwksp_reserve_internal(ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_reserve_internal() argument
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/linux-6.6.21/Documentation/devicetree/bindings/mmc/
Dsamsung,exynos-dw-mshc.yaml54 - description: CIU clock phase shift value for tx mode
57 - description: CIU clock phase shift value for rx mode
61 The value of CUI clock phase shift value in transmit mode and CIU clock
62 phase shift value in receive mode for double data rate mode operation.
68 - description: CIU clock phase shift value for tx mode
71 - description: CIU clock phase shift value for rx mode
75 The value of CIU TX and RX clock phase shift value for HS400 mode
78 - valid value for tx phase shift and rx phase shift is 0 to 7.
79 - when CIU clock divider value is set to 3, all possible 8 phase shift
82 phase shift clocks should be 0.
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/linux-6.6.21/drivers/parport/
Dieee1284_ops.c52 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_write_compat()
138 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_write_compat()
171 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_nibble()
221 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_nibble()
224 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_nibble()
259 port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_byte()
306 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_byte()
309 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_byte()
345 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in ecp_forward_to_reverse()
348 port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; in ecp_forward_to_reverse()
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/linux-6.6.21/drivers/net/wwan/iosm/
Diosm_ipc_imem_ops.c19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
68 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_transmit()
146 enum ipc_phase phase; in ipc_imem_is_channel_active() local
149 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
152 switch (phase) { in ipc_imem_is_channel_active()
174 channel->channel_id, phase); in ipc_imem_is_channel_active()
203 curr_phase = ipc_imem->phase; in ipc_imem_sys_port_close()
294 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_port_open()
[all …]
Diosm_ipc_imem.c291 ipc_imem_phase_get_string(ipc_imem->phase), in ipc_imem_ipc_init_check()
540 return (ipc_imem->phase == IPC_P_RUN && in ipc_imem_get_exec_stage_buffered()
572 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_run_state_worker()
645 enum ipc_phase old_phase, phase; in ipc_imem_handle_irq() local
654 old_phase = ipc_imem->phase; in ipc_imem_handle_irq()
664 phase = ipc_imem_phase_update(ipc_imem); in ipc_imem_handle_irq()
666 switch (phase) { in ipc_imem_handle_irq()
704 ipc_imem_phase_get_string(phase)); in ipc_imem_handle_irq()
772 if ((phase == IPC_P_PSI || phase == IPC_P_EBL) && in ipc_imem_handle_irq()
814 if (ipc_imem->phase != IPC_P_ROM) { in ipc_imem_phase_update_check()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_dccg.c53 int phase; in dccg21_update_dpp_dto() local
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
85 phase = 10; in dccg21_update_dpp_dto()
89 DPPCLK0_DTO_PHASE, phase, in dccg21_update_dpp_dto()
/linux-6.6.21/fs/
Dfsopen.c142 fc->phase = FS_CONTEXT_CREATE_PARAMS; in SYSCALL_DEFINE2()
195 fc->phase = FS_CONTEXT_RECONF_PARAMS; in SYSCALL_DEFINE3()
217 if (fc->phase != FS_CONTEXT_CREATE_PARAMS) in vfs_cmd_create()
227 fc->phase = FS_CONTEXT_CREATING; in vfs_cmd_create()
232 fc->phase = FS_CONTEXT_FAILED; in vfs_cmd_create()
240 fc->phase = FS_CONTEXT_FAILED; in vfs_cmd_create()
246 fc->phase = FS_CONTEXT_AWAITING_MOUNT; in vfs_cmd_create()
255 if (fc->phase != FS_CONTEXT_RECONF_PARAMS) in vfs_cmd_reconfigure()
258 fc->phase = FS_CONTEXT_RECONFIGURING; in vfs_cmd_reconfigure()
262 fc->phase = FS_CONTEXT_FAILED; in vfs_cmd_reconfigure()
[all …]
/linux-6.6.21/drivers/char/ipmi/
Dkcs_bmc_cdev_ipmi.c76 enum kcs_ipmi_phases phase; member
133 priv->phase = KCS_PHASE_ERROR; in kcs_bmc_ipmi_force_abort()
145 switch (priv->phase) { in kcs_bmc_ipmi_handle_data()
147 priv->phase = KCS_PHASE_WRITE_DATA; in kcs_bmc_ipmi_handle_data()
165 priv->phase = KCS_PHASE_WRITE_DONE; in kcs_bmc_ipmi_handle_data()
187 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
198 priv->phase = KCS_PHASE_ABORT_ERROR2; in kcs_bmc_ipmi_handle_data()
205 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
224 priv->phase = KCS_PHASE_WRITE_START; in kcs_bmc_ipmi_handle_cmd()
231 if (priv->phase != KCS_PHASE_WRITE_DATA) { in kcs_bmc_ipmi_handle_cmd()
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/linux-6.6.21/include/trace/events/
Dclk.h200 TP_PROTO(struct clk_core *core, int phase),
202 TP_ARGS(core, phase),
206 __field( int, phase )
211 __entry->phase = phase;
214 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
219 TP_PROTO(struct clk_core *core, int phase),
221 TP_ARGS(core, phase)
226 TP_PROTO(struct clk_core *core, int phase),
228 TP_ARGS(core, phase)
/linux-6.6.21/drivers/scsi/pcmcia/
Dnsp_cs.c231 scsi_pointer->phase = PH_UNDETERMINED; in nsp_queuecommand_lck()
371 unsigned char phase, arbit; in nsphw_start_selection() local
375 phase = nsp_index_read(base, SCSIBUSMON); in nsphw_start_selection()
376 if(phase != BUSMON_BUS_FREE) { in nsphw_start_selection()
383 scsi_pointer->phase = PH_ARBSTART; in nsphw_start_selection()
403 scsi_pointer->phase = PH_SELSTART; in nsphw_start_selection()
548 unsigned char phase, i_src; in nsp_expect_signal() local
554 phase = nsp_index_read(base, SCSIBUSMON); in nsp_expect_signal()
555 if (phase == 0xff) { in nsp_expect_signal()
564 if ((phase & mask) != 0 && (phase & BUSMON_PHASE_MASK) == current_phase) { in nsp_expect_signal()
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/spi/
Dsamsung,spi-peripheral-props.yaml23 The sampling phase shift to be applied on the miso line (to account
25 - 0: No phase shift.
26 - 1: 90 degree phase shift sampling.
27 - 2: 180 degree phase shift sampling.
28 - 3: 270 degree phase shift sampling.
/linux-6.6.21/drivers/mmc/core/
Dhost.c224 struct mmc_clk_phase *phase) in mmc_of_parse_timing_phase() argument
230 phase->valid = !rc; in mmc_of_parse_timing_phase()
231 if (phase->valid) { in mmc_of_parse_timing_phase()
232 phase->in_deg = degrees[0]; in mmc_of_parse_timing_phase()
233 phase->out_deg = degrees[1]; in mmc_of_parse_timing_phase()
243 &map->phase[MMC_TIMING_LEGACY]); in mmc_of_parse_clk_phase()
245 &map->phase[MMC_TIMING_MMC_HS]); in mmc_of_parse_clk_phase()
247 &map->phase[MMC_TIMING_SD_HS]); in mmc_of_parse_clk_phase()
249 &map->phase[MMC_TIMING_UHS_SDR12]); in mmc_of_parse_clk_phase()
251 &map->phase[MMC_TIMING_UHS_SDR25]); in mmc_of_parse_clk_phase()
[all …]
/linux-6.6.21/drivers/leds/trigger/
Dledtrig-heartbeat.c27 unsigned int phase; member
52 switch (heartbeat_data->phase) { in led_heartbeat_function()
65 heartbeat_data->phase++; in led_heartbeat_function()
71 heartbeat_data->phase++; in led_heartbeat_function()
77 heartbeat_data->phase++; in led_heartbeat_function()
84 heartbeat_data->phase = 0; in led_heartbeat_function()
140 heartbeat_data->phase = 0; in heartbeat_trig_activate()
/linux-6.6.21/drivers/infiniband/hw/efa/
Defa_com.c142 sq->phase = 1; in efa_com_admin_init_sq()
178 cq->phase = 1; in efa_com_admin_init_cq()
219 aenq->phase = 1; in efa_com_admin_init_aenq()
324 EFA_ADMIN_AQ_COMMON_DESC_PHASE, aq->sq.phase); in __efa_com_submit_admin_cmd()
347 aq->sq.phase = !aq->sq.phase; in __efa_com_submit_admin_cmd()
438 u8 phase; in efa_com_handle_admin_completion() local
444 phase = aq->cq.phase; in efa_com_handle_admin_completion()
450 EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { in efa_com_handle_admin_completion()
462 phase = !phase; in efa_com_handle_admin_completion()
469 aq->cq.phase = phase; in efa_com_handle_admin_completion()
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