Searched refs:output_width (Results 1 – 5 of 5) sorted by relevance
| /linux-6.6.21/drivers/staging/media/ipu3/ |
| D | ipu3-css-params.c | 45 unsigned int output_width, int phase_step_correction, in imgu_css_scaler_setup_lut() argument
50 int exponent = imgu_css_scaler_get_exp(output_width, input_width); in imgu_css_scaler_setup_lut()
51 int mantissa = (1 << exponent) * output_width; in imgu_css_scaler_setup_lut()
54 if (input_width == output_width) { in imgu_css_scaler_setup_lut()
90 output_width / input_width; in imgu_css_scaler_setup_lut()
138 unsigned int *output_width, unsigned int *output_height, in imgu_css_scaler_calc() argument
189 *output_width = out_width; in imgu_css_scaler_calc()
351 int output_width[IMGU_ABI_OSYS_PINS]; member
370 unsigned int output_width, pin, s; in imgu_css_osys_calc_frame_and_stripe_params() local
482 output_width = reso.pin_width[IMGU_ABI_OSYS_PIN_VF]; in imgu_css_osys_calc_frame_and_stripe_params()
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| D | ipu3-abi.h | 1041 u32 output_width[IMGU_ABI_OSYS_PINS]; member
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| /linux-6.6.21/drivers/media/platform/verisilicon/ |
| D | hantro_postproc.c | 47 .output_width = {G1_REG_PP_CONTROL, 4, 0x7ff},
102 HANTRO_PP_REG_WRITE(vpu, output_width, ctx->dst_fmt.width); in hantro_postproc_g1_enable()
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| D | hantro.h | 319 struct hantro_reg output_width; member
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| /linux-6.6.21/drivers/gpu/drm/arm/ |
| D | malidp_drv.c | 711 u8 output_width[MAX_OUTPUT_CHANNELS]; in malidp_bind() local
802 output_width, MAX_OUTPUT_CHANNELS); in malidp_bind()
807 out_depth = (out_depth << 8) | (output_width[i] & 0xf); in malidp_bind()
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