| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_mpc.c | 149 unsigned int opp_id; in mpc1_is_mpcc_idle() local
153 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
155 if (top_sel == 0xf && opp_id == 0xf && idle) in mpc1_is_mpcc_idle()
237 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
240 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id); in mpc1_insert_plane()
246 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); in mpc1_insert_plane()
302 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); in mpc1_remove_mpcc()
306 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); in mpc1_remove_mpcc()
375 int opp_id; in mpc1_mpc_init() local
387 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { in mpc1_mpc_init()
[all …]
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| D | dcn10_mpc.h | 201 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
203 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
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| D | dcn10_hw_sequencer.h | 68 int opp_id);
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| D | dcn10_hw_sequencer_debug.c | 400 if (s.opp_id != 0xf) { in dcn10_get_mpcc_states()
402 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_get_mpcc_states()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_optc.c | 50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc314_set_odm_combine() argument
74 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc314_set_odm_combine()
76 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc314_set_odm_combine()
87 OPTC_SEG0_SRC_SEL, opp_id[0], in optc314_set_odm_combine()
88 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc314_set_odm_combine()
92 OPTC_SEG0_SRC_SEL, opp_id[0], in optc314_set_odm_combine()
93 OPTC_SEG1_SRC_SEL, opp_id[1], in optc314_set_odm_combine()
94 OPTC_SEG2_SRC_SEL, opp_id[2], in optc314_set_odm_combine()
95 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc314_set_odm_combine()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_optc.c | 43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc31_set_odm_combine() argument
61 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc31_set_odm_combine()
63 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc31_set_odm_combine()
76 OPTC_SEG0_SRC_SEL, opp_id[0], in optc31_set_odm_combine()
77 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc31_set_odm_combine()
81 OPTC_SEG0_SRC_SEL, opp_id[0], in optc31_set_odm_combine()
82 OPTC_SEG1_SRC_SEL, opp_id[1], in optc31_set_odm_combine()
83 OPTC_SEG2_SRC_SEL, opp_id[2], in optc31_set_odm_combine()
84 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc31_set_odm_combine()
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| D | dcn31_hubp.c | 109 hubp2->base.opp_id = OPP_ID_INVALID; in hubp31_construct()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | mpc.h | 173 int opp_id; /* The OPP instance that owns this MPC tree */ member
187 uint32_t opp_id; member
298 int opp_id,
361 int opp_id,
366 int opp_id,
370 int opp_id,
375 int opp_id,
402 int opp_id,
433 int opp_id);
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| D | hubp.h | 64 int opp_id; member
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| D | timing_generator.h | 310 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_optc.c | 45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc32_set_odm_combine() argument
69 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc32_set_odm_combine()
71 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc32_set_odm_combine()
82 OPTC_SEG0_SRC_SEL, opp_id[0], in optc32_set_odm_combine()
83 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc32_set_odm_combine()
87 OPTC_SEG0_SRC_SEL, opp_id[0], in optc32_set_odm_combine()
88 OPTC_SEG1_SRC_SEL, opp_id[1], in optc32_set_odm_combine()
89 OPTC_SEG2_SRC_SEL, opp_id[2], in optc32_set_odm_combine()
90 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc32_set_odm_combine()
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| D | dcn32_hubp.c | 221 hubp2->base.opp_id = OPP_ID_INVALID; in hubp32_construct()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_optc.c | 218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
243 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc3_set_odm_combine()
248 …memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (o… in optc3_set_odm_combine()
258 OPTC_SEG0_SRC_SEL, opp_id[0], in optc3_set_odm_combine()
259 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc3_set_odm_combine()
263 OPTC_SEG0_SRC_SEL, opp_id[0], in optc3_set_odm_combine()
264 OPTC_SEG1_SRC_SEL, opp_id[1], in optc3_set_odm_combine()
265 OPTC_SEG2_SRC_SEL, opp_id[2], in optc3_set_odm_combine()
266 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc3_set_odm_combine()
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| D | dcn30_mpc.c | 85 int opp_id, in mpc3_set_out_rate_control() argument
92 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
97 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
380 int opp_id, in mpc3_set_denorm() argument
413 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc3_set_denorm()
419 int opp_id, in mpc3_set_denorm_clamp() argument
425 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc3_set_denorm_clamp()
428 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc3_set_denorm_clamp()
431 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc3_set_denorm_clamp()
1236 int opp_id, in mpc3_set_output_csc() argument
[all …]
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| D | dcn30_mpc.h | 1026 int opp_id,
1031 int opp_id,
1036 int opp_id,
1042 int opp_id,
1080 int opp_id,
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.c | 75 int opp_id, in mpc2_set_denorm() argument
107 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc2_set_denorm()
113 int opp_id, in mpc2_set_denorm_clamp() argument
118 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc2_set_denorm_clamp()
121 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc2_set_denorm_clamp()
124 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc2_set_denorm_clamp()
133 int opp_id, in mpc2_set_output_csc() argument
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
[all …]
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| D | dcn20_optc.c | 188 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
211 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc2_set_odm_combine()
219 OPTC_SEG0_SRC_SEL, opp_id[0], in optc2_set_odm_combine()
220 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc2_set_odm_combine()
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| D | dcn20_mpc.h | 284 int opp_id,
289 int opp_id,
294 int opp_id,
300 int opp_id,
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| D | dcn20_hwseq.h | 51 int opp_id);
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| D | dcn20_optc.h | 107 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_mpc.c | 44 int opp_id, in mpc201_set_out_rate_control() argument
51 REG_UPDATE_2(MUX[opp_id], in mpc201_set_out_rate_control()
56 REG_UPDATE_3(MUX[opp_id], in mpc201_set_out_rate_control()
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| D | dcn201_hubp.c | 145 hubp201->base.opp_id = OPP_ID_INVALID; in dcn201_hubp_construct()
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| D | dcn201_hwseq.c | 295 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn201_init_hw()
314 hubp->opp_id = OPP_ID_INVALID; in dcn201_init_hw()
517 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_hw_sequencer.c | 575 …block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp-… in hwss_build_fast_sequence()
582 …block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.op… in hwss_build_fast_sequence()
767 int opp_id = params->set_output_csc_params.opp_id; in hwss_set_output_csc() local
773 opp_id, in hwss_set_output_csc()
781 int opp_id = params->set_ocsc_default_params.opp_id; in hwss_set_ocsc_default() local
787 opp_id, in hwss_set_ocsc_default()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer.h | 125 int opp_id; member
132 int opp_id; member
292 uint16_t *matrix, int opp_id);
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