Searched refs:num_tile_mode_states (Results 1 – 5 of 5) sorted by relevance
385 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v6_0_tiling_mode_table_init() local626 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()832 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()1056 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()1280 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
2077 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init() local2084 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2252 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2444 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2633 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2836 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3038 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3207 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3384 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
989 const u32 num_tile_mode_states = in gfx_v7_0_tiling_mode_table_init() local1012 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1179 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1362 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1532 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
2324 const u32 num_tile_mode_states = in cik_tiling_mode_table_init() local2350 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2493 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2636 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2861 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()3004 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2491 const u32 num_tile_mode_states = in si_tiling_mode_table_init() local2508 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()2722 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()2937 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()