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Searched refs:mmVGA_RENDER_CONTROL (Results 1 – 22 of 22) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c244 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v6_0_mc_program()
246 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v6_0_mc_program()
Dcik.c980 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in cik_read_disabled_bios()
994 WREG32(mmVGA_RENDER_CONTROL, in cik_read_disabled_bios()
1006 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); in cik_read_disabled_bios()
Dvi.c603 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in vi_read_disabled_bios()
617 WREG32(mmVGA_RENDER_CONTROL, in vi_read_disabled_bios()
629 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); in vi_read_disabled_bios()
Dgmc_v7_0.c279 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
281 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v7_0_mc_program()
Dgmc_v8_0.c453 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v8_0_mc_program()
455 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v8_0_mc_program()
Ddce_v6_0.c360 WREG32(mmVGA_RENDER_CONTROL, in dce_v6_0_set_vga_render_state()
361 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); in dce_v6_0_set_vga_render_state()
Ddce_v8_0.c391 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v8_0_set_vga_render_state()
396 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v8_0_set_vga_render_state()
Ddce_v10_0.c454 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_set_vga_render_state()
459 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
Ddce_v11_0.c476 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_set_vga_render_state()
481 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v11_0_set_vga_render_state()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h4393 #define mmVGA_RENDER_CONTROL 0x00C0 macro
Ddce_8_0_d.h5133 #define mmVGA_RENDER_CONTROL 0xc0 macro
Ddce_10_0_d.h6016 #define mmVGA_RENDER_CONTROL 0xc0 macro
Ddce_11_0_d.h6093 #define mmVGA_RENDER_CONTROL 0xc0 macro
Ddce_11_2_d.h7767 #define mmVGA_RENDER_CONTROL 0xc0 macro
Ddce_12_0_offset.h554 #define mmVGA_RENDER_CONTROL macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h17 #define mmVGA_RENDER_CONTROL macro
Ddcn_3_0_1_offset.h148 #define mmVGA_RENDER_CONTROL macro
Ddcn_2_1_0_offset.h88 #define mmVGA_RENDER_CONTROL macro
Ddcn_1_0_offset.h388 #define mmVGA_RENDER_CONTROL macro
Ddcn_3_0_2_offset.h32 #define mmVGA_RENDER_CONTROL macro
Ddcn_2_0_0_offset.h32 #define mmVGA_RENDER_CONTROL macro
Ddcn_3_0_0_offset.h14 #define mmVGA_RENDER_CONTROL macro