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Searched refs:mmUVD_RB_RPTR (Results 1 – 12 of 12) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h47 #define mmUVD_RB_RPTR 0x3c29 macro
Duvd_7_0_offset.h100 #define mmUVD_RB_RPTR … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h222 #define mmUVD_RB_RPTR … macro
Dvcn_2_5_offset.h557 #define mmUVD_RB_RPTR … macro
Dvcn_2_0_0_offset.h934 #define mmUVD_RB_RPTR … macro
Dvcn_3_0_0_offset.h887 #define mmUVD_RB_RPTR … macro
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c1084 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1115 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1554 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); in vcn_v2_0_enc_ring_get_rptr()
Dvcn_v1_0.c945 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1593 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); in vcn_v1_0_enc_ring_get_rptr()
Dvcn_v2_5.c1136 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1362 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1490 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1615 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v2_5_enc_ring_get_rptr()
Dvcn_v3_0.c1261 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1504 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1640 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1940 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v3_0_enc_ring_get_rptr()
Duvd_v6_0.c96 return RREG32(mmUVD_RB_RPTR); in uvd_v6_0_enc_ring_get_rptr()
863 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
Duvd_v7_0.c90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in uvd_v7_0_enc_ring_get_rptr()
1114 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()