1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_TPC6_CFG_REGS_H_ 14 #define ASIC_REG_TPC6_CFG_REGS_H_ 15 16 /* 17 ***************************************** 18 * TPC6_CFG (Prototype: TPC) 19 ***************************************** 20 */ 21 22 #define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400 23 24 #define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404 25 26 #define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408 27 28 #define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C 29 30 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410 31 32 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414 33 34 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF86418 35 36 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF8641C 37 38 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86420 39 40 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF86424 41 42 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86428 43 44 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF8642C 45 46 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86430 47 48 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86434 49 50 #define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF86438 51 52 #define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF8643C 53 54 #define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86440 55 56 #define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86444 57 58 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF86448 59 60 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF8644C 61 62 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86450 63 64 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF86454 65 66 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86458 67 68 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF8645C 69 70 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86460 71 72 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86464 73 74 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF86468 75 76 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF8646C 77 78 #define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86470 79 80 #define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF86474 81 82 #define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF86478 83 84 #define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF8647C 85 86 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF86480 87 88 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF86484 89 90 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF86488 91 92 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF8648C 93 94 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF86490 95 96 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF86494 97 98 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF86498 99 100 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF8649C 101 102 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864A0 103 104 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864A4 105 106 #define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864A8 107 108 #define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864AC 109 110 #define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864B0 111 112 #define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864B4 113 114 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864B8 115 116 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864BC 117 118 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF864C0 119 120 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF864C4 121 122 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF864C8 123 124 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF864CC 125 126 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF864D0 127 128 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF864D4 129 130 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF864D8 131 132 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF864DC 133 134 #define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF864E0 135 136 #define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF864E4 137 138 #define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF864E8 139 140 #define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF864EC 141 142 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF864F0 143 144 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF864F4 145 146 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF864F8 147 148 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF864FC 149 150 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86500 151 152 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF86504 153 154 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86508 155 156 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF8650C 157 158 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86510 159 160 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86514 161 162 #define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF86518 163 164 #define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF8651C 165 166 #define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86520 167 168 #define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86524 169 170 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF86528 171 172 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF8652C 173 174 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86530 175 176 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF86534 177 178 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF86538 179 180 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF8653C 181 182 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF86540 183 184 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF86544 185 186 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF86548 187 188 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF8654C 189 190 #define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF86550 191 192 #define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF86554 193 194 #define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF86558 195 196 #define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF8655C 197 198 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF86560 199 200 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF86564 201 202 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF86568 203 204 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF8656C 205 206 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF86570 207 208 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF86574 209 210 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF86578 211 212 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF8657C 213 214 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86580 215 216 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF86584 217 218 #define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86588 219 220 #define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF8658C 221 222 #define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF86590 223 224 #define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86594 225 226 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86598 227 228 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF8659C 229 230 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF865A0 231 232 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF865A4 233 234 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF865A8 235 236 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF865AC 237 238 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF865B0 239 240 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF865B4 241 242 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF865B8 243 244 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF865BC 245 246 #define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF865C0 247 248 #define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF865C4 249 250 #define mmTPC6_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF865C8 251 252 #define mmTPC6_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF865CC 253 254 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF865D0 255 256 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF865D4 257 258 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF865D8 259 260 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF865DC 261 262 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF865E0 263 264 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF865E4 265 266 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF865E8 267 268 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF865EC 269 270 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF865F0 271 272 #define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF865F4 273 274 #define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF865F8 275 276 #define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF865FC 277 278 #define mmTPC6_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF86600 279 280 #define mmTPC6_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF86604 281 282 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF86608 283 284 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF8660C 285 286 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF86610 287 288 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF86614 289 290 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF86618 291 292 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF8661C 293 294 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF86620 295 296 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF86624 297 298 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF86628 299 300 #define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF8662C 301 302 #define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF86630 303 304 #define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF86634 305 306 #define mmTPC6_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF86638 307 308 #define mmTPC6_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF8663C 309 310 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF86640 311 312 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF86644 313 314 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF86648 315 316 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF8664C 317 318 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF86650 319 320 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF86654 321 322 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF86658 323 324 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF8665C 325 326 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF86660 327 328 #define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF86664 329 330 #define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF86668 331 332 #define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF8666C 333 334 #define mmTPC6_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF86670 335 336 #define mmTPC6_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF86674 337 338 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF86678 339 340 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF8667C 341 342 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF86680 343 344 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF86684 345 346 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF86688 347 348 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF8668C 349 350 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF86690 351 352 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF86694 353 354 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF86698 355 356 #define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF8669C 357 358 #define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF866A0 359 360 #define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF866A4 361 362 #define mmTPC6_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF866A8 363 364 #define mmTPC6_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF866AC 365 366 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF866B0 367 368 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF866B4 369 370 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF866B8 371 372 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF866BC 373 374 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF866C0 375 376 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF866C4 377 378 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF866C8 379 380 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF866CC 381 382 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF866D0 383 384 #define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF866D4 385 386 #define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF866D8 387 388 #define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF866DC 389 390 #define mmTPC6_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF866E0 391 392 #define mmTPC6_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF866E4 393 394 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF866E8 395 396 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF866EC 397 398 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF866F0 399 400 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF866F4 401 402 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF866F8 403 404 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF866FC 405 406 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF86700 407 408 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF86704 409 410 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF86708 411 412 #define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF8670C 413 414 #define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF86710 415 416 #define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF86714 417 418 #define mmTPC6_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF86718 419 420 #define mmTPC6_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF8671C 421 422 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF86720 423 424 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF86724 425 426 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF86728 427 428 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF8672C 429 430 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF86730 431 432 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF86734 433 434 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF86738 435 436 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF8673C 437 438 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF86740 439 440 #define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF86744 441 442 #define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF86748 443 444 #define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF8674C 445 446 #define mmTPC6_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF86750 447 448 #define mmTPC6_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF86754 449 450 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF86758 451 452 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF8675C 453 454 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF86760 455 456 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF86764 457 458 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF86768 459 460 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF8676C 461 462 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF86770 463 464 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF86774 465 466 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF86778 467 468 #define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF8677C 469 470 #define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86780 471 472 #define mmTPC6_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF86784 473 474 #define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86788 475 476 #define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF8678C 477 478 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86790 479 480 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF86794 481 482 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86798 483 484 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF8679C 485 486 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF867A0 487 488 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF867A4 489 490 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF867A8 491 492 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF867AC 493 494 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF867B0 495 496 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF867B4 497 498 #define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF867B8 499 500 #define mmTPC6_CFG_KERNEL_KERNEL_ID 0xF867BC 501 502 #define mmTPC6_CFG_KERNEL_SRF_0 0xF867C0 503 504 #define mmTPC6_CFG_KERNEL_SRF_1 0xF867C4 505 506 #define mmTPC6_CFG_KERNEL_SRF_2 0xF867C8 507 508 #define mmTPC6_CFG_KERNEL_SRF_3 0xF867CC 509 510 #define mmTPC6_CFG_KERNEL_SRF_4 0xF867D0 511 512 #define mmTPC6_CFG_KERNEL_SRF_5 0xF867D4 513 514 #define mmTPC6_CFG_KERNEL_SRF_6 0xF867D8 515 516 #define mmTPC6_CFG_KERNEL_SRF_7 0xF867DC 517 518 #define mmTPC6_CFG_KERNEL_SRF_8 0xF867E0 519 520 #define mmTPC6_CFG_KERNEL_SRF_9 0xF867E4 521 522 #define mmTPC6_CFG_KERNEL_SRF_10 0xF867E8 523 524 #define mmTPC6_CFG_KERNEL_SRF_11 0xF867EC 525 526 #define mmTPC6_CFG_KERNEL_SRF_12 0xF867F0 527 528 #define mmTPC6_CFG_KERNEL_SRF_13 0xF867F4 529 530 #define mmTPC6_CFG_KERNEL_SRF_14 0xF867F8 531 532 #define mmTPC6_CFG_KERNEL_SRF_15 0xF867FC 533 534 #define mmTPC6_CFG_KERNEL_SRF_16 0xF86800 535 536 #define mmTPC6_CFG_KERNEL_SRF_17 0xF86804 537 538 #define mmTPC6_CFG_KERNEL_SRF_18 0xF86808 539 540 #define mmTPC6_CFG_KERNEL_SRF_19 0xF8680C 541 542 #define mmTPC6_CFG_KERNEL_SRF_20 0xF86810 543 544 #define mmTPC6_CFG_KERNEL_SRF_21 0xF86814 545 546 #define mmTPC6_CFG_KERNEL_SRF_22 0xF86818 547 548 #define mmTPC6_CFG_KERNEL_SRF_23 0xF8681C 549 550 #define mmTPC6_CFG_KERNEL_SRF_24 0xF86820 551 552 #define mmTPC6_CFG_KERNEL_SRF_25 0xF86824 553 554 #define mmTPC6_CFG_KERNEL_SRF_26 0xF86828 555 556 #define mmTPC6_CFG_KERNEL_SRF_27 0xF8682C 557 558 #define mmTPC6_CFG_KERNEL_SRF_28 0xF86830 559 560 #define mmTPC6_CFG_KERNEL_SRF_29 0xF86834 561 562 #define mmTPC6_CFG_KERNEL_SRF_30 0xF86838 563 564 #define mmTPC6_CFG_KERNEL_SRF_31 0xF8683C 565 566 #define mmTPC6_CFG_ROUND_CSR 0xF868FC 567 568 #define mmTPC6_CFG_PROT 0xF86900 569 570 #define mmTPC6_CFG_SEMAPHORE 0xF86908 571 572 #define mmTPC6_CFG_VFLAGS 0xF8690C 573 574 #define mmTPC6_CFG_SFLAGS 0xF86910 575 576 #define mmTPC6_CFG_LFSR_POLYNOM 0xF86918 577 578 #define mmTPC6_CFG_STATUS 0xF8691C 579 580 #define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86920 581 582 #define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86924 583 584 #define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8692C 585 586 #define mmTPC6_CFG_TPC_CMD 0xF86930 587 588 #define mmTPC6_CFG_TPC_EXECUTE 0xF86938 589 590 #define mmTPC6_CFG_TPC_STALL 0xF8693C 591 592 #define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86940 593 594 #define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86944 595 596 #define mmTPC6_CFG_RD_RATE_LIMIT 0xF86948 597 598 #define mmTPC6_CFG_WR_RATE_LIMIT 0xF86950 599 600 #define mmTPC6_CFG_MSS_CONFIG 0xF86954 601 602 #define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86958 603 604 #define mmTPC6_CFG_TPC_INTR_MASK 0xF8695C 605 606 #define mmTPC6_CFG_WQ_CREDITS 0xF86960 607 608 #define mmTPC6_CFG_ARUSER_LO 0xF86964 609 610 #define mmTPC6_CFG_ARUSER_HI 0xF86968 611 612 #define mmTPC6_CFG_AWUSER_LO 0xF8696C 613 614 #define mmTPC6_CFG_AWUSER_HI 0xF86970 615 616 #define mmTPC6_CFG_OPCODE_EXEC 0xF86974 617 618 #define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF86978 619 620 #define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF8697C 621 622 #define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF86980 623 624 #define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF86984 625 626 #define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF86988 627 628 #define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF8698C 629 630 #define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF86990 631 632 #define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF86994 633 634 #define mmTPC6_CFG_TSB_CFG_MAX_SIZE 0xF86998 635 636 #define mmTPC6_CFG_TSB_CFG 0xF8699C 637 638 #define mmTPC6_CFG_DBGMEM_ADD 0xF869A0 639 640 #define mmTPC6_CFG_DBGMEM_DATA_WR 0xF869A4 641 642 #define mmTPC6_CFG_DBGMEM_DATA_RD 0xF869A8 643 644 #define mmTPC6_CFG_DBGMEM_CTRL 0xF869AC 645 646 #define mmTPC6_CFG_DBGMEM_RC 0xF869B0 647 648 #define mmTPC6_CFG_TSB_INFLIGHT_CNTR 0xF869B4 649 650 #define mmTPC6_CFG_WQ_INFLIGHT_CNTR 0xF869B8 651 652 #define mmTPC6_CFG_WQ_LBW_TOTAL_CNTR 0xF869BC 653 654 #define mmTPC6_CFG_WQ_HBW_TOTAL_CNTR 0xF869C0 655 656 #define mmTPC6_CFG_IRQ_OCCOUPY_CNTR 0xF869C4 657 658 #define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF869D0 659 660 #define mmTPC6_CFG_FUNC_MBIST_PAT 0xF869D4 661 662 #define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF869D8 663 664 #define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF869DC 665 666 #define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF869E0 667 668 #define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF869E4 669 670 #define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF869E8 671 672 #define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF869EC 673 674 #define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF869F0 675 676 #define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF869F4 677 678 #define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF869F8 679 680 #define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF869FC 681 682 #define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00 683 684 #define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04 685 686 #define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08 687 688 #define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C 689 690 #define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10 691 692 #define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14 693 694 #define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A18 695 696 #define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A1C 697 698 #define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A20 699 700 #define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A24 701 702 #define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A28 703 704 #define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A2C 705 706 #define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A30 707 708 #define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A34 709 710 #define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A38 711 712 #define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A3C 713 714 #define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A40 715 716 #define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A44 717 718 #define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A48 719 720 #define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A4C 721 722 #define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A50 723 724 #define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A54 725 726 #define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A58 727 728 #define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A5C 729 730 #define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A60 731 732 #define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A64 733 734 #define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A68 735 736 #define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A6C 737 738 #define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A70 739 740 #define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A74 741 742 #define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86A78 743 744 #define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86A7C 745 746 #define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86A80 747 748 #define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86A84 749 750 #define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86A88 751 752 #define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86A8C 753 754 #define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86A90 755 756 #define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86A94 757 758 #define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86A98 759 760 #define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86A9C 761 762 #define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AA0 763 764 #define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86AA4 765 766 #define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AA8 767 768 #define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AAC 769 770 #define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AB0 771 772 #define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AB4 773 774 #define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AB8 775 776 #define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86ABC 777 778 #define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86AC0 779 780 #define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86AC4 781 782 #define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86AC8 783 784 #define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86ACC 785 786 #define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86AD0 787 788 #define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86AD4 789 790 #define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86AD8 791 792 #define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86ADC 793 794 #define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86AE0 795 796 #define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86AE4 797 798 #define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86AE8 799 800 #define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86AEC 801 802 #define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86AF0 803 804 #define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86AF4 805 806 #define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86AF8 807 808 #define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86AFC 809 810 #define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B00 811 812 #define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B04 813 814 #define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B08 815 816 #define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B0C 817 818 #define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B10 819 820 #define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B14 821 822 #define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B18 823 824 #define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B1C 825 826 #define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B20 827 828 #define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B24 829 830 #define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B28 831 832 #define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B2C 833 834 #define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B30 835 836 #define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B34 837 838 #define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86B38 839 840 #define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86B3C 841 842 #define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86B40 843 844 #define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86B44 845 846 #define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86B48 847 848 #define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86B4C 849 850 #define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86B50 851 852 #define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86B54 853 854 #define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86B58 855 856 #define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86B5C 857 858 #define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86B60 859 860 #define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86B64 861 862 #define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86B68 863 864 #define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86B6C 865 866 #define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86B70 867 868 #define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86B74 869 870 #define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86B78 871 872 #define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86B7C 873 874 #define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86B80 875 876 #define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86B84 877 878 #define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86B88 879 880 #define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86B8C 881 882 #define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86B90 883 884 #define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86B94 885 886 #define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86B98 887 888 #define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86B9C 889 890 #define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86BA0 891 892 #define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86BA4 893 894 #define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86BA8 895 896 #define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86BAC 897 898 #define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86BB0 899 900 #define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86BB4 901 902 #define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86BB8 903 904 #define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86BBC 905 906 #define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF86BC0 907 908 #define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF86BC4 909 910 #define mmTPC6_CFG_QM_TENSOR_8_PADDING_VALUE 0xF86BC8 911 912 #define mmTPC6_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF86BCC 913 914 #define mmTPC6_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF86BD0 915 916 #define mmTPC6_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF86BD4 917 918 #define mmTPC6_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF86BD8 919 920 #define mmTPC6_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF86BDC 921 922 #define mmTPC6_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF86BE0 923 924 #define mmTPC6_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF86BE4 925 926 #define mmTPC6_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF86BE8 927 928 #define mmTPC6_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF86BEC 929 930 #define mmTPC6_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF86BF0 931 932 #define mmTPC6_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF86BF4 933 934 #define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF86BF8 935 936 #define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF86BFC 937 938 #define mmTPC6_CFG_QM_TENSOR_9_PADDING_VALUE 0xF86C00 939 940 #define mmTPC6_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF86C04 941 942 #define mmTPC6_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF86C08 943 944 #define mmTPC6_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF86C0C 945 946 #define mmTPC6_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF86C10 947 948 #define mmTPC6_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF86C14 949 950 #define mmTPC6_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF86C18 951 952 #define mmTPC6_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF86C1C 953 954 #define mmTPC6_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF86C20 955 956 #define mmTPC6_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF86C24 957 958 #define mmTPC6_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF86C28 959 960 #define mmTPC6_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF86C2C 961 962 #define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF86C30 963 964 #define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF86C34 965 966 #define mmTPC6_CFG_QM_TENSOR_10_PADDING_VALUE 0xF86C38 967 968 #define mmTPC6_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF86C3C 969 970 #define mmTPC6_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF86C40 971 972 #define mmTPC6_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF86C44 973 974 #define mmTPC6_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF86C48 975 976 #define mmTPC6_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF86C4C 977 978 #define mmTPC6_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF86C50 979 980 #define mmTPC6_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF86C54 981 982 #define mmTPC6_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF86C58 983 984 #define mmTPC6_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF86C5C 985 986 #define mmTPC6_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF86C60 987 988 #define mmTPC6_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF86C64 989 990 #define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF86C68 991 992 #define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF86C6C 993 994 #define mmTPC6_CFG_QM_TENSOR_11_PADDING_VALUE 0xF86C70 995 996 #define mmTPC6_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF86C74 997 998 #define mmTPC6_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF86C78 999 1000 #define mmTPC6_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF86C7C 1001 1002 #define mmTPC6_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF86C80 1003 1004 #define mmTPC6_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF86C84 1005 1006 #define mmTPC6_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF86C88 1007 1008 #define mmTPC6_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF86C8C 1009 1010 #define mmTPC6_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF86C90 1011 1012 #define mmTPC6_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF86C94 1013 1014 #define mmTPC6_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF86C98 1015 1016 #define mmTPC6_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF86C9C 1017 1018 #define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF86CA0 1019 1020 #define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF86CA4 1021 1022 #define mmTPC6_CFG_QM_TENSOR_12_PADDING_VALUE 0xF86CA8 1023 1024 #define mmTPC6_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF86CAC 1025 1026 #define mmTPC6_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF86CB0 1027 1028 #define mmTPC6_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF86CB4 1029 1030 #define mmTPC6_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF86CB8 1031 1032 #define mmTPC6_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF86CBC 1033 1034 #define mmTPC6_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF86CC0 1035 1036 #define mmTPC6_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF86CC4 1037 1038 #define mmTPC6_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF86CC8 1039 1040 #define mmTPC6_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF86CCC 1041 1042 #define mmTPC6_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF86CD0 1043 1044 #define mmTPC6_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF86CD4 1045 1046 #define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF86CD8 1047 1048 #define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF86CDC 1049 1050 #define mmTPC6_CFG_QM_TENSOR_13_PADDING_VALUE 0xF86CE0 1051 1052 #define mmTPC6_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF86CE4 1053 1054 #define mmTPC6_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF86CE8 1055 1056 #define mmTPC6_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF86CEC 1057 1058 #define mmTPC6_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF86CF0 1059 1060 #define mmTPC6_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF86CF4 1061 1062 #define mmTPC6_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF86CF8 1063 1064 #define mmTPC6_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF86CFC 1065 1066 #define mmTPC6_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF86D00 1067 1068 #define mmTPC6_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF86D04 1069 1070 #define mmTPC6_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF86D08 1071 1072 #define mmTPC6_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF86D0C 1073 1074 #define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF86D10 1075 1076 #define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF86D14 1077 1078 #define mmTPC6_CFG_QM_TENSOR_14_PADDING_VALUE 0xF86D18 1079 1080 #define mmTPC6_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF86D1C 1081 1082 #define mmTPC6_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF86D20 1083 1084 #define mmTPC6_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF86D24 1085 1086 #define mmTPC6_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF86D28 1087 1088 #define mmTPC6_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF86D2C 1089 1090 #define mmTPC6_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF86D30 1091 1092 #define mmTPC6_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF86D34 1093 1094 #define mmTPC6_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF86D38 1095 1096 #define mmTPC6_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF86D3C 1097 1098 #define mmTPC6_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF86D40 1099 1100 #define mmTPC6_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF86D44 1101 1102 #define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF86D48 1103 1104 #define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF86D4C 1105 1106 #define mmTPC6_CFG_QM_TENSOR_15_PADDING_VALUE 0xF86D50 1107 1108 #define mmTPC6_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF86D54 1109 1110 #define mmTPC6_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF86D58 1111 1112 #define mmTPC6_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF86D5C 1113 1114 #define mmTPC6_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF86D60 1115 1116 #define mmTPC6_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF86D64 1117 1118 #define mmTPC6_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF86D68 1119 1120 #define mmTPC6_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF86D6C 1121 1122 #define mmTPC6_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF86D70 1123 1124 #define mmTPC6_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF86D74 1125 1126 #define mmTPC6_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF86D78 1127 1128 #define mmTPC6_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF86D7C 1129 1130 #define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D80 1131 1132 #define mmTPC6_CFG_QM_SYNC_OBJECT_ADDR 0xF86D84 1133 1134 #define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86D88 1135 1136 #define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86D8C 1137 1138 #define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86D90 1139 1140 #define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86D94 1141 1142 #define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86D98 1143 1144 #define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86D9C 1145 1146 #define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86DA0 1147 1148 #define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86DA4 1149 1150 #define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86DA8 1151 1152 #define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86DAC 1153 1154 #define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86DB0 1155 1156 #define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86DB4 1157 1158 #define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86DB8 1159 1160 #define mmTPC6_CFG_QM_KERNEL_ID 0xF86DBC 1161 1162 #define mmTPC6_CFG_QM_SRF_0 0xF86DC0 1163 1164 #define mmTPC6_CFG_QM_SRF_1 0xF86DC4 1165 1166 #define mmTPC6_CFG_QM_SRF_2 0xF86DC8 1167 1168 #define mmTPC6_CFG_QM_SRF_3 0xF86DCC 1169 1170 #define mmTPC6_CFG_QM_SRF_4 0xF86DD0 1171 1172 #define mmTPC6_CFG_QM_SRF_5 0xF86DD4 1173 1174 #define mmTPC6_CFG_QM_SRF_6 0xF86DD8 1175 1176 #define mmTPC6_CFG_QM_SRF_7 0xF86DDC 1177 1178 #define mmTPC6_CFG_QM_SRF_8 0xF86DE0 1179 1180 #define mmTPC6_CFG_QM_SRF_9 0xF86DE4 1181 1182 #define mmTPC6_CFG_QM_SRF_10 0xF86DE8 1183 1184 #define mmTPC6_CFG_QM_SRF_11 0xF86DEC 1185 1186 #define mmTPC6_CFG_QM_SRF_12 0xF86DF0 1187 1188 #define mmTPC6_CFG_QM_SRF_13 0xF86DF4 1189 1190 #define mmTPC6_CFG_QM_SRF_14 0xF86DF8 1191 1192 #define mmTPC6_CFG_QM_SRF_15 0xF86DFC 1193 1194 #define mmTPC6_CFG_QM_SRF_16 0xF86E00 1195 1196 #define mmTPC6_CFG_QM_SRF_17 0xF86E04 1197 1198 #define mmTPC6_CFG_QM_SRF_18 0xF86E08 1199 1200 #define mmTPC6_CFG_QM_SRF_19 0xF86E0C 1201 1202 #define mmTPC6_CFG_QM_SRF_20 0xF86E10 1203 1204 #define mmTPC6_CFG_QM_SRF_21 0xF86E14 1205 1206 #define mmTPC6_CFG_QM_SRF_22 0xF86E18 1207 1208 #define mmTPC6_CFG_QM_SRF_23 0xF86E1C 1209 1210 #define mmTPC6_CFG_QM_SRF_24 0xF86E20 1211 1212 #define mmTPC6_CFG_QM_SRF_25 0xF86E24 1213 1214 #define mmTPC6_CFG_QM_SRF_26 0xF86E28 1215 1216 #define mmTPC6_CFG_QM_SRF_27 0xF86E2C 1217 1218 #define mmTPC6_CFG_QM_SRF_28 0xF86E30 1219 1220 #define mmTPC6_CFG_QM_SRF_29 0xF86E34 1221 1222 #define mmTPC6_CFG_QM_SRF_30 0xF86E38 1223 1224 #define mmTPC6_CFG_QM_SRF_31 0xF86E3C 1225 1226 #endif /* ASIC_REG_TPC6_CFG_REGS_H_ */ 1227