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Searched refs:mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h423 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX … macro
Dsdma0_4_0_offset.h511 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 macro
Dsdma0_4_2_2_offset.h511 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX … macro
Dsdma0_4_2_offset.h507 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h501 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX … macro
Dgc_10_3_0_offset.h505 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX … macro