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Searched refs:mmRLC_SRM_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/pm/powerplay/inc/
Dpolaris10_pwrvirus.h50 { 0x00000002, mmRLC_SRM_CNTL },
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_d.h1452 #define mmRLC_SRM_CNTL 0xec80 macro
Dgfx_8_1_d.h1448 #define mmRLC_SRM_CNTL 0xec80 macro
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c2562 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); in gfx_v9_1_init_rlc_save_restore_list()
2564 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); in gfx_v9_1_init_rlc_save_restore_list()
Dgfx_v10_0.c5107 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); in gfx_v10_0_rlc_enable_srm()
5110 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); in gfx_v10_0_rlc_enable_srm()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6141 #define mmRLC_SRM_CNTL macro
Dgc_9_1_offset.h6363 #define mmRLC_SRM_CNTL macro
Dgc_9_2_1_offset.h6339 #define mmRLC_SRM_CNTL macro
Dgc_10_1_0_offset.h9473 #define mmRLC_SRM_CNTL macro
Dgc_10_3_0_offset.h9307 #define mmRLC_SRM_CNTL macro