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Searched refs:mmGC_DIDT_CTRL0 (Results 1 – 5 of 5) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega10_powertune.c577 …{ mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, GC_DIDT_CTRL0__DIDT_CTRL…
578 …{ mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__PHASE_OFFSET_MASK, GC_DIDT_CTRL0__PHASE_OFF…
579 …{ mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_SW_RST_MASK, GC_DIDT_CTRL0__DIDT_SW_RS…
580 …{ mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, GC_DIDT_CTRL0__D…
581 …{ mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, GC_DIDT_…
986 cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data); in vega10_disable_psm_gc_didt_config()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2959 #define mmGC_DIDT_CTRL0 … macro
Dgc_9_1_offset.h3191 #define mmGC_DIDT_CTRL0 … macro
Dgc_9_2_1_offset.h3147 #define mmGC_DIDT_CTRL0 … macro
Dgc_10_1_0_offset.h5457 #define mmGC_DIDT_CTRL0 … macro