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Searched refs:mmDP3_DP_DPHY_TRAINING_PATTERN_SEL (Results 1 – 12 of 12) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h3285 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45D1 macro
Ddce_8_0_d.h3879 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1 macro
Ddce_10_0_d.h4511 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 macro
Ddce_11_0_d.h4491 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 macro
Ddce_11_2_d.h5723 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 macro
Ddce_12_0_offset.h11078 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_1_offset.h8970 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_2_1_0_offset.h10873 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_1_0_offset.h9309 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_3_0_2_offset.h10592 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_2_0_0_offset.h11960 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_3_0_0_offset.h11728 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … macro