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Searched refs:mmDP1_DP_DPHY_CRC_CNTL (Results 1 – 14 of 14) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h3170 #define mmDP1_DP_DPHY_CRC_CNTL 0x1FD7 macro
Ddce_8_0_d.h3941 #define mmDP1_DP_DPHY_CRC_CNTL 0x1fd7 macro
Ddce_10_0_d.h4573 #define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 macro
Ddce_11_0_d.h4578 #define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 macro
Ddce_11_2_d.h5810 #define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 macro
Ddce_12_0_offset.h10526 #define mmDP1_DP_DPHY_CRC_CNTL … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h5830 #define mmDP1_DP_DPHY_CRC_CNTL … macro
Ddcn_3_0_3_offset.h5339 #define mmDP1_DP_DPHY_CRC_CNTL … macro
Ddcn_3_0_1_offset.h8306 #define mmDP1_DP_DPHY_CRC_CNTL … macro
Ddcn_2_1_0_offset.h10229 #define mmDP1_DP_DPHY_CRC_CNTL … macro
Ddcn_1_0_offset.h8705 #define mmDP1_DP_DPHY_CRC_CNTL … macro
Ddcn_3_0_2_offset.h9921 #define mmDP1_DP_DPHY_CRC_CNTL … macro
Ddcn_2_0_0_offset.h11320 #define mmDP1_DP_DPHY_CRC_CNTL … macro
Ddcn_3_0_0_offset.h11057 #define mmDP1_DP_DPHY_CRC_CNTL … macro