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Searched refs:mmDP0_DP_DPHY_TRAINING_PATTERN_SEL (Results 1 – 14 of 14) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h3129 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 macro
Ddce_8_0_d.h3876 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 macro
Ddce_10_0_d.h4508 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 macro
Ddce_11_0_d.h4488 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 macro
Ddce_11_2_d.h5720 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 macro
Ddce_12_0_offset.h10226 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h5494 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_3_0_3_offset.h4980 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_3_0_1_offset.h7950 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_2_1_0_offset.h9883 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_1_0_offset.h8379 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_3_0_2_offset.h9562 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_2_0_0_offset.h10976 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro
Ddcn_3_0_0_offset.h10698 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … macro