1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ 14 #define ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ 15 16 /* 17 ***************************************** 18 * DMA_IF_W_S_DOWN_CH0 (Prototype: RTR_CTRL) 19 ***************************************** 20 */ 21 22 #define mmDMA_IF_W_S_DOWN_CH0_PERM_SEL 0x481108 23 24 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_0 0x481114 25 26 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_1 0x481118 27 28 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_2 0x48111C 29 30 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_3 0x481120 31 32 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_4 0x481124 33 34 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_5 0x481128 35 36 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_6 0x48112C 37 38 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_7 0x481130 39 40 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_8 0x481134 41 42 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_9 0x481138 43 44 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_10 0x48113C 45 46 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_11 0x481140 47 48 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_12 0x481144 49 50 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_13 0x481148 51 52 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_14 0x48114C 53 54 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_15 0x481150 55 56 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_16 0x481154 57 58 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_17 0x481158 59 60 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_18 0x48115C 61 62 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_19 0x481160 63 64 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_20 0x481164 65 66 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_21 0x481168 67 68 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_22 0x48116C 69 70 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_23 0x481170 71 72 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_24 0x481174 73 74 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_25 0x481178 75 76 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_26 0x48117C 77 78 #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_27 0x481180 79 80 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_0 0x481184 81 82 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_1 0x481188 83 84 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_2 0x48118C 85 86 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_3 0x481190 87 88 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_4 0x481194 89 90 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_5 0x481198 91 92 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_6 0x48119C 93 94 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_7 0x4811A0 95 96 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_8 0x4811A4 97 98 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_9 0x4811A8 99 100 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_10 0x4811AC 101 102 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_11 0x4811B0 103 104 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_12 0x4811B4 105 106 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_13 0x4811B8 107 108 #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_14 0x4811BC 109 110 #define mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN 0x48126C 111 112 #define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN 0x481274 113 114 #define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT 0x481278 115 116 #define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST 0x48127C 117 118 #define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT 0x481280 119 120 #define mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN 0x481284 121 122 #define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_EN 0x481288 123 124 #define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_SAT 0x48128C 125 126 #define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_RST 0x481290 127 128 #define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_TIMEOUT 0x481294 129 130 #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN 0x48129C 131 132 #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT 0x4812A0 133 134 #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST 0x4812A4 135 136 #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4812AC 137 138 #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RED 0x4812B4 139 140 #define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN 0x4812EC 141 142 #define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN 0x4812F0 143 144 #define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4812F4 145 146 #define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4812F8 147 148 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x481404 149 150 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x481408 151 152 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x48140C 153 154 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x481410 155 156 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x481414 157 158 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x481418 159 160 #define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x48141C 161 162 #define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x481420 163 164 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x481424 165 166 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x481428 167 168 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x48142C 169 170 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x481430 171 172 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x481434 173 174 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x481438 175 176 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0 0x481450 177 178 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1 0x481454 179 180 #define mmDMA_IF_W_S_DOWN_CH0_NON_LIN_EN 0x481480 181 182 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_0 0x481500 183 184 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_1 0x481504 185 186 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_2 0x481508 187 188 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_3 0x48150C 189 190 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_4 0x481510 191 192 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x481514 193 194 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x481520 195 196 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x481524 197 198 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x481528 199 200 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x48152C 201 202 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x481530 203 204 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x481534 205 206 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x481538 207 208 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x48153C 209 210 #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x481540 211 212 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_0 0x481550 213 214 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_1 0x481554 215 216 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_2 0x481558 217 218 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_3 0x48155C 219 220 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_4 0x481560 221 222 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_5 0x481564 223 224 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_6 0x481568 225 226 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_7 0x48156C 227 228 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_8 0x481570 229 230 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_9 0x481574 231 232 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_10 0x481578 233 234 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_11 0x48157C 235 236 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_12 0x481580 237 238 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_13 0x481584 239 240 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_14 0x481588 241 242 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_15 0x48158C 243 244 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_16 0x481590 245 246 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_17 0x481594 247 248 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18 0x481598 249 250 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4815E4 251 252 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4815E8 253 254 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4815EC 255 256 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4815F0 257 258 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4815F4 259 260 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4815F8 261 262 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4815FC 263 264 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x481600 265 266 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x481604 267 268 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x481608 269 270 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x48160C 271 272 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x481610 273 274 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x481614 275 276 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x481618 277 278 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x48161C 279 280 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x481620 281 282 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x481624 283 284 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x481628 285 286 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x48162C 287 288 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x481630 289 290 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x481634 291 292 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x481638 293 294 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x48163C 295 296 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x481640 297 298 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x481644 299 300 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x481648 301 302 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x48164C 303 304 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x481650 305 306 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x481654 307 308 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x481658 309 310 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x48165C 311 312 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x481660 313 314 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x481664 315 316 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x481668 317 318 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x48166C 319 320 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x481670 321 322 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x481674 323 324 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x481678 325 326 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x48167C 327 328 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x481680 329 330 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x481684 331 332 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x481688 333 334 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x48168C 335 336 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x481690 337 338 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x481694 339 340 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x481698 341 342 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x48169C 343 344 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4816A0 345 346 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4816A4 347 348 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4816A8 349 350 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4816AC 351 352 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4816B0 353 354 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4816B4 355 356 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4816B8 357 358 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4816BC 359 360 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4816C0 361 362 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4816C4 363 364 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4816C8 365 366 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4816CC 367 368 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4816D0 369 370 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4816D4 371 372 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4816D8 373 374 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4816DC 375 376 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4816E0 377 378 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4816E4 379 380 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4816E8 381 382 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4816EC 383 384 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4816F0 385 386 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4816F4 387 388 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4816F8 389 390 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4816FC 391 392 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x481700 393 394 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x481704 395 396 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x481708 397 398 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x48170C 399 400 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x481710 401 402 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x481714 403 404 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x481718 405 406 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x48171C 407 408 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x481720 409 410 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x481724 411 412 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x481728 413 414 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x48172C 415 416 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x481730 417 418 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x481734 419 420 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x481738 421 422 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x48173C 423 424 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x481740 425 426 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x481744 427 428 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x481748 429 430 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x48174C 431 432 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x481750 433 434 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x481754 435 436 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x481758 437 438 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x48175C 439 440 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x481760 441 442 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x481764 443 444 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x481768 445 446 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x48176C 447 448 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x481770 449 450 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x481774 451 452 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x481778 453 454 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x48177C 455 456 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x481780 457 458 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x481784 459 460 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x481788 461 462 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x48178C 463 464 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x481790 465 466 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x481794 467 468 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x481798 469 470 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x48179C 471 472 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4817A0 473 474 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4817A4 475 476 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4817A8 477 478 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4817AC 479 480 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4817B0 481 482 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4817B4 483 484 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4817B8 485 486 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4817BC 487 488 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4817C0 489 490 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4817C4 491 492 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4817C8 493 494 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4817CC 495 496 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4817D0 497 498 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4817D4 499 500 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4817D8 501 502 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4817DC 503 504 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4817E0 505 506 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x481824 507 508 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x481828 509 510 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x48182C 511 512 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x481830 513 514 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x481834 515 516 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x481838 517 518 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x48183C 519 520 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x481840 521 522 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x481844 523 524 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x481848 525 526 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x48184C 527 528 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x481850 529 530 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x481854 531 532 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x481858 533 534 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x48185C 535 536 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x481860 537 538 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x481864 539 540 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x481868 541 542 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x48186C 543 544 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x481870 545 546 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x481874 547 548 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x481878 549 550 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x48187C 551 552 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x481880 553 554 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x481884 555 556 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x481888 557 558 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x48188C 559 560 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x481890 561 562 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x481894 563 564 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x481898 565 566 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x48189C 567 568 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4818A0 569 570 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4818A4 571 572 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4818A8 573 574 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4818AC 575 576 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4818B0 577 578 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4818B4 579 580 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4818B8 581 582 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4818BC 583 584 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4818C0 585 586 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4818C4 587 588 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4818C8 589 590 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4818CC 591 592 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4818D0 593 594 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4818D4 595 596 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4818D8 597 598 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4818DC 599 600 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4818E0 601 602 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4818E4 603 604 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4818E8 605 606 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4818EC 607 608 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4818F0 609 610 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4818F4 611 612 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4818F8 613 614 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4818FC 615 616 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x481900 617 618 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x481904 619 620 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x481908 621 622 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x48190C 623 624 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x481910 625 626 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x481914 627 628 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x481918 629 630 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x48191C 631 632 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x481920 633 634 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x481924 635 636 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x481928 637 638 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x48192C 639 640 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x481930 641 642 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x481934 643 644 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x481938 645 646 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x48193C 647 648 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x481940 649 650 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x481944 651 652 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x481948 653 654 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x48194C 655 656 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x481950 657 658 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x481954 659 660 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x481958 661 662 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x48195C 663 664 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x481960 665 666 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x481964 667 668 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x481968 669 670 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x48196C 671 672 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x481970 673 674 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x481974 675 676 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x481978 677 678 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x48197C 679 680 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x481980 681 682 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x481984 683 684 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x481988 685 686 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x48198C 687 688 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x481990 689 690 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x481994 691 692 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x481998 693 694 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x48199C 695 696 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4819A0 697 698 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4819A4 699 700 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4819A8 701 702 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4819AC 703 704 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4819B0 705 706 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4819B4 707 708 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4819B8 709 710 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4819BC 711 712 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4819C0 713 714 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4819C4 715 716 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4819C8 717 718 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4819CC 719 720 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4819D0 721 722 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4819D4 723 724 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4819D8 725 726 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4819DC 727 728 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4819E0 729 730 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4819E4 731 732 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4819E8 733 734 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4819EC 735 736 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4819F0 737 738 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4819F4 739 740 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4819F8 741 742 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4819FC 743 744 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x481A00 745 746 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x481A04 747 748 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x481A08 749 750 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x481A0C 751 752 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x481A10 753 754 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x481A14 755 756 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x481A18 757 758 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x481A1C 759 760 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x481A20 761 762 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x481A64 763 764 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x481A68 765 766 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x481A6C 767 768 #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x481A70 769 770 #define mmDMA_IF_W_S_DOWN_CH0_RGL_CFG 0x481B64 771 772 #define mmDMA_IF_W_S_DOWN_CH0_RGL_SHIFT 0x481B68 773 774 #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x481B6C 775 776 #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x481B70 777 778 #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x481B74 779 780 #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x481B78 781 782 #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x481B7C 783 784 #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x481B80 785 786 #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x481B84 787 788 #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x481B88 789 790 #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_0 0x481BAC 791 792 #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_1 0x481BB0 793 794 #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_2 0x481BB4 795 796 #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_3 0x481BB8 797 798 #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_4 0x481BBC 799 800 #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_5 0x481BC0 801 802 #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_6 0x481BC4 803 804 #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_7 0x481BC8 805 806 #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_0 0x481BEC 807 808 #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_1 0x481BF0 809 810 #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_2 0x481BF4 811 812 #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_3 0x481BF8 813 814 #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_4 0x481BFC 815 816 #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_5 0x481C00 817 818 #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_6 0x481C04 819 820 #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_7 0x481C08 821 822 #define mmDMA_IF_W_S_DOWN_CH0_RGL_WDT 0x481C2C 823 824 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x481C30 825 826 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x481C34 827 828 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x481C38 829 830 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x481C3C 831 832 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x481C40 833 834 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x481C44 835 836 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x481C48 837 838 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x481C4C 839 840 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x481C50 841 842 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x481C54 843 844 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x481C58 845 846 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x481C5C 847 848 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x481C60 849 850 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x481C64 851 852 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x481C68 853 854 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x481C6C 855 856 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x481C70 857 858 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x481C74 859 860 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x481C78 861 862 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x481C7C 863 864 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x481C80 865 866 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x481C84 867 868 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x481C88 869 870 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x481C8C 871 872 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x481C90 873 874 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x481C94 875 876 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x481C98 877 878 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x481C9C 879 880 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x481CA0 881 882 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x481CA4 883 884 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x481CA8 885 886 #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x481CAC 887 888 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x481CB0 889 890 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x481CB4 891 892 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x481CB8 893 894 #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x481CBC 895 896 #endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ */ 897