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Searched refs:mmDIG1_TMDS_STEREOSYNC_CTL_SEL (Results 1 – 14 of 14) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h2645 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1F7F macro
Ddce_8_0_d.h3425 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f macro
Ddce_10_0_d.h4204 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e macro
Ddce_11_0_d.h4139 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e macro
Ddce_11_2_d.h5370 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e macro
Ddce_12_0_offset.h10456 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h5754 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro
Ddcn_3_0_3_offset.h5266 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro
Ddcn_3_0_1_offset.h8236 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro
Ddcn_2_1_0_offset.h10149 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro
Ddcn_1_0_offset.h8633 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro
Ddcn_3_0_2_offset.h9848 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro
Ddcn_2_0_0_offset.h11242 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro
Ddcn_3_0_0_offset.h10984 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … macro