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Searched refs:mmDIG0_TMDS_DCBALANCER_CONTROL (Results 1 – 14 of 14) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h2558 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1C84 macro
Ddce_8_0_d.h3464 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84 macro
Ddce_10_0_d.h4243 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 macro
Ddce_11_0_d.h4188 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 macro
Ddce_11_2_d.h5419 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 macro
Ddce_12_0_offset.h10180 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h5442 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro
Ddcn_3_0_3_offset.h4931 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro
Ddcn_3_0_1_offset.h7904 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro
Ddcn_2_1_0_offset.h9827 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro
Ddcn_1_0_offset.h8331 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro
Ddcn_3_0_2_offset.h9513 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro
Ddcn_2_0_0_offset.h10922 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro
Ddcn_3_0_0_offset.h10649 #define mmDIG0_TMDS_DCBALANCER_CONTROL … macro