Searched refs:mmDC_HPD_INT_CONTROL (Results 1 – 5 of 5) sorted by relevance
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/ |
D | dce_v10_0.c | 310 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity() 315 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity() 347 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init() 349 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init() 3057 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state() 3059 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state() 3062 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state() 3064 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state() 3207 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack() 3209 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
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D | dce_v11_0.c | 334 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_set_polarity() 339 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_set_polarity() 371 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init() 373 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init() 3188 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state() 3190 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state() 3193 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state() 3195 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state() 3338 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack() 3340 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_int_ack()
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/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/ |
D | dce_10_0_d.h | 7096 #define mmDC_HPD_INT_CONTROL 0x1899 macro
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D | dce_11_0_d.h | 7282 #define mmDC_HPD_INT_CONTROL 0x1899 macro
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D | dce_11_2_d.h | 8663 #define mmDC_HPD_INT_CONTROL 0x1899 macro
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