Searched refs:mmDCORE0_TPC0_QM_BASE (Results 1 – 4 of 4) sorted by relevance
171 #define DCORE_OFFSET (mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE)173 #define DCORE_TPC_OFFSET (mmDCORE0_TPC1_QM_BASE - mmDCORE0_TPC0_QM_BASE)
5950 #define mmDCORE0_TPC0_QM_BASE 0x400A000ull macro
1017 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = mmDCORE0_TPC0_QM_BASE,1018 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = mmDCORE0_TPC0_QM_BASE,1019 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = mmDCORE0_TPC0_QM_BASE,1020 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = mmDCORE0_TPC0_QM_BASE,5361 gaudi2_init_qman(hdev, mmDCORE0_TPC0_QM_BASE + offset, queue_id_base); in gaudi2_init_tpc_config()7787 glbl_sts_addr = qman_base + (mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 - mmDCORE0_TPC0_QM_BASE); in gaudi2_handle_qman_err_generic()7788 arb_err_addr = qman_base + (mmDCORE0_TPC0_QM_ARB_ERR_CAUSE - mmDCORE0_TPC0_QM_BASE); in gaudi2_handle_qman_err_generic()8319 qman_base = mmDCORE0_TPC0_QM_BASE + in gaudi2_handle_qm_sei_err()8381 qman_base = mmDCORE0_TPC0_QM_BASE + index * DCORE_TPC_OFFSET; in gaudi2_handle_qman_err()
1245 mmDCORE0_TPC0_QM_BASE,