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Searched refs:mmCP_HQD_PQ_CONTROL (Results 1 – 15 of 15) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/pm/powerplay/inc/
Dpolaris10_pwrvirus.h1513 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1523 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1533 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1543 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dmes_v10_1.c778 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
Dgfx_v9_0.c3322 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); in gfx_v9_0_mqd_init()
3433 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, in gfx_v9_0_kiq_init_register()
Dgfx_v7_0.c2891 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
Dgfx_v10_0.c6565 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); in gfx_v10_0_compute_mqd_init()
6675 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, in gfx_v10_0_kiq_init_register()
Dgfx_v8_0.c4463 tmp = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v8_0_mqd_init()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h584 #define mmCP_HQD_PQ_CONTROL 0x3256 macro
Dgfx_7_2_d.h597 #define mmCP_HQD_PQ_CONTROL 0x3256 macro
Dgfx_8_0_d.h647 #define mmCP_HQD_PQ_CONTROL 0x3256 macro
Dgfx_8_1_d.h647 #define mmCP_HQD_PQ_CONTROL 0x3256 macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2851 #define mmCP_HQD_PQ_CONTROL macro
Dgc_9_1_offset.h3079 #define mmCP_HQD_PQ_CONTROL macro
Dgc_9_2_1_offset.h3035 #define mmCP_HQD_PQ_CONTROL macro
Dgc_10_1_0_offset.h5333 #define mmCP_HQD_PQ_CONTROL macro
Dgc_10_3_0_offset.h4968 #define mmCP_HQD_PQ_CONTROL macro