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Searched refs:mmCP_HQD_IB_CONTROL (Results 1 – 13 of 13) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gca/ !
Dgfx_7_0_d.h588 #define mmCP_HQD_IB_CONTROL 0x325a macro
Dgfx_7_2_d.h601 #define mmCP_HQD_IB_CONTROL 0x325a macro
Dgfx_8_0_d.h651 #define mmCP_HQD_IB_CONTROL 0x325a macro
Dgfx_8_1_d.h651 #define mmCP_HQD_IB_CONTROL 0x325a macro
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/ !
Dgfx_v9_0.c3359 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in gfx_v9_0_mqd_init()
3518 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); in gfx_v9_0_kiq_fini_register()
Dgfx_v7_0.c2951 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v7_0_mqd_init()
Dgfx_v8_0.c4518 tmp = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v8_0_mqd_init()
Dgfx_v10_0.c6601 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in gfx_v10_0_compute_mqd_init()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/ !
Dgc_9_0_offset.h2859 #define mmCP_HQD_IB_CONTROL … macro
Dgc_9_1_offset.h3087 #define mmCP_HQD_IB_CONTROL … macro
Dgc_9_2_1_offset.h3043 #define mmCP_HQD_IB_CONTROL … macro
Dgc_10_1_0_offset.h5341 #define mmCP_HQD_IB_CONTROL … macro
Dgc_10_3_0_offset.h4976 #define mmCP_HQD_IB_CONTROL … macro