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Searched refs:mmCP_HQD_HQ_SCHEDULER0_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2884 #define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX … macro
Dgc_9_1_offset.h3112 #define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX … macro
Dgc_9_2_1_offset.h3068 #define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX … macro
Dgc_10_1_0_offset.h5366 #define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX … macro
Dgc_10_3_0_offset.h5001 #define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX … macro