| /linux-6.6.21/drivers/tty/serial/ |
| D | milbeaut_usio.c | 67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
82 port->membase + MLB_USIO_REG_SCR); in mlb_usio_tx_chars()
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR); in mlb_usio_tx_chars()
96 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff); in mlb_usio_tx_chars()
[all …]
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| D | xilinx_uartps.c | 232 while ((readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_rx()
235 rxbs_status = readl(port->membase + CDNS_UART_RXBS); in cdns_uart_handle_rx()
236 data = readl(port->membase + CDNS_UART_FIFO); in cdns_uart_handle_rx()
320 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); in cdns_uart_handle_tx()
326 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { in cdns_uart_handle_tx()
328 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO); in cdns_uart_handle_tx()
354 isrstatus = readl(port->membase + CDNS_UART_ISR); in cdns_uart_isr()
355 writel(isrstatus, port->membase + CDNS_UART_ISR); in cdns_uart_isr()
369 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) in cdns_uart_isr()
458 mreg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_baud_rate()
[all …]
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| D | mcf.c | 62 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? in mcf_tx_empty()
73 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? in mcf_get_mctrl()
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_set_mctrl()
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); in mcf_set_mctrl()
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); in mcf_start_tx()
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_start_tx()
109 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_start_tx()
119 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_tx()
129 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_rx()
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); in mcf_break_ctl()
[all …]
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| D | timbuart.c | 42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
64 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty()
72 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | in timbuart_flush_buffer()
75 iowrite8(ctl, port->membase + TIMBUART_CTRL); in timbuart_flush_buffer()
76 iowrite32(TXBF, port->membase + TIMBUART_ISR); in timbuart_flush_buffer()
84 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { in timbuart_rx_chars()
85 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); in timbuart_rx_chars()
[all …]
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| D | meson_uart.c | 102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
111 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
113 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
120 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
122 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
134 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
137 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
153 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
155 writel(port->x_char, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
165 writel(ch, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
[all …]
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| D | qcom_geni_serial.c | 193 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
194 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
195 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
196 port->se.base = uport->membase; in qcom_geni_serial_request_port()
216 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; in qcom_geni_serial_main_active()
265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; in qcom_geni_serial_secondary_active()
297 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bit()
310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
[all …]
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| D | lpc32xx_hs.c | 103 port->membase))) == 0) in wait_for_xmit_empty()
117 port->membase))) < 32) in wait_for_xmit_ready()
128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
168 if (!port->membase) in lpc32xx_hsuart_console_setup()
246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
248 readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
265 LPC32XX_HSUART_IIR(port->membase)); in __serial_lpc32xx_rx()
273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
281 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase)); in serial_lpc32xx_tx_ready()
[all …]
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| D | amba-pl010.c | 65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
67 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
78 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
89 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
97 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
99 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
108 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
110 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
[all …]
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| D | fsl_linflexuart.c | 147 ier = readl(port->membase + LINIER); in linflex_stop_tx()
149 writel(ier, port->membase + LINIER); in linflex_stop_tx()
156 ier = readl(port->membase + LINIER); in linflex_stop_rx()
157 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER); in linflex_stop_rx()
164 writeb(c, sport->membase + BDRL); in linflex_put_char()
167 while (((status = readl(sport->membase + UARTSR)) & in linflex_put_char()
172 writel(status | LINFLEXD_UARTSR_DTFTFF, sport->membase + UARTSR); in linflex_put_char()
196 ier = readl(port->membase + LINIER); in linflex_start_tx()
197 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER); in linflex_start_tx()
235 status = readl(sport->membase + UARTSR); in linflex_rxint()
[all …]
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| D | digicolor-usart.c | 85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); in digicolor_rx_poll()
144 ch = readb_relaxed(port->membase + UA_EMI_REC); in digicolor_uart_rx()
[all …]
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| D | mvebu-uart.c | 191 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
229 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
231 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
238 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
240 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
242 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
244 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
[all …]
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| D | sunplus-uart.c | 82 writel(ch, port->membase + SUP_UART_DATA); in sp_uart_put_char()
87 unsigned int lsr = readl(port->membase + SUP_UART_LSR); in sunplus_tx_buf_not_full()
94 unsigned int lsr = readl(port->membase + SUP_UART_LSR); in sunplus_tx_empty()
101 unsigned int mcr = readl(port->membase + SUP_UART_MCR); in sunplus_set_mctrl()
128 writel(mcr, port->membase + SUP_UART_MCR); in sunplus_set_mctrl()
135 mcr = readl(port->membase + SUP_UART_MCR); in sunplus_get_mctrl()
159 isc = readl(port->membase + SUP_UART_ISC); in sunplus_stop_tx()
161 writel(isc, port->membase + SUP_UART_ISC); in sunplus_stop_tx()
168 isc = readl(port->membase + SUP_UART_ISC); in sunplus_start_tx()
170 writel(isc, port->membase + SUP_UART_ISC); in sunplus_start_tx()
[all …]
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| D | lantiq.c | 144 u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT); in lqasc_tx_ready()
159 writeb(ch, port->membase + LTQ_ASC_TBUF)); in lqasc_start_tx()
167 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
176 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
180 ch = readb(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
181 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
194 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
198 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
203 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
240 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); in lqasc_tx_int()
[all …]
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| D | fsl_lpuart.c | 386 return readl(port->membase + off); in lpuart32_read()
388 return ioread32be(port->membase + off); in lpuart32_read()
399 writel(val, port->membase + off); in lpuart32_write()
402 iowrite32be(val, port->membase + off); in lpuart32_write()
444 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
446 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
462 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
463 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
623 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
625 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
[all …]
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| D | altera_jtaguart.c | 55 u32 ctl = readl(port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_tx_space()
81 port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_start_tx()
88 port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_tx()
95 port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_rx()
116 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & in altera_jtaguart_rx_chars()
138 writel(ch, port->membase + ALTERA_JTAGUART_DATA_REG), in altera_jtaguart_tx_chars()
147 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> in altera_jtaguart_interrupt()
167 writel(0, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_config_port()
188 port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_startup()
204 port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_shutdown()
[all …]
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| /linux-6.6.21/drivers/atm/ |
| D | idt77252.h | 355 void __iomem *membase; /* SAR's memory base address */ member
441 #define SAR_REG_DR0 (card->membase + 0x00)
442 #define SAR_REG_DR1 (card->membase + 0x04)
443 #define SAR_REG_DR2 (card->membase + 0x08)
444 #define SAR_REG_DR3 (card->membase + 0x0C)
445 #define SAR_REG_CMD (card->membase + 0x10)
446 #define SAR_REG_CFG (card->membase + 0x14)
447 #define SAR_REG_STAT (card->membase + 0x18)
448 #define SAR_REG_RSQB (card->membase + 0x1C)
449 #define SAR_REG_RSQT (card->membase + 0x20)
[all …]
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| /linux-6.6.21/drivers/net/mdio/ |
| D | mdio-ipq4019.c | 41 void __iomem *membase; member
51 return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy, in ipq4019_mdio_wait_busy()
66 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c45()
70 writel(data, priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c45()
73 writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); in ipq4019_mdio_read_c45()
76 writel(reg, priv->membase + MDIO_DATA_WRITE_REG); in ipq4019_mdio_read_c45()
81 writel(cmd, priv->membase + MDIO_CMD_REG); in ipq4019_mdio_read_c45()
89 writel(cmd, priv->membase + MDIO_CMD_REG); in ipq4019_mdio_read_c45()
95 return readl(priv->membase + MDIO_DATA_READ_REG); in ipq4019_mdio_read_c45()
107 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c22()
[all …]
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| D | mdio-sun4i.c | 32 void __iomem *membase; member
43 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_read()
45 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
49 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_read()
56 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
58 value = readl(data->membase + EMAC_MAC_MRDD_REG); in sun4i_mdio_read()
70 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_write()
72 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
76 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_write()
83 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
[all …]
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| /linux-6.6.21/drivers/net/ethernet/allwinner/ |
| D | sun4i-emac.c | 77 void __iomem *membase; member
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
203 writel(0, db->membase + EMAC_CTL_REG); in emac_reset()
205 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset()
261 reg_val = readl(db->membase + EMAC_RX_CTL_REG); in emac_dma_done_callback()
263 writel(reg_val, db->membase + EMAC_RX_CTL_REG); in emac_dma_done_callback()
266 reg_val = readl(db->membase + EMAC_INT_CTL_REG); in emac_dma_done_callback()
[all …]
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| /linux-6.6.21/drivers/gpio/ |
| D | gpio-timberdale.c | 35 void __iomem *membase; member
50 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
57 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
73 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
110 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_disable()
122 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_enable()
138 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
142 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
143 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
145 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
[all …]
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| D | gpio-sa1100.c | 19 void __iomem *membase; member
42 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
50 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
55 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
65 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_input()
77 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_output()
105 .membase = (void *)&GPLR,
116 void *base = sgc->membase; in sa1100_update_edge_regs()
158 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); in sa1100_gpio_ack()
234 void __iomem *gedr = sgc->membase + R_GEDR; in sa1100_gpio_handler()
[all …]
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| /linux-6.6.21/drivers/i2c/busses/ |
| D | i2c-uniphier-f.c | 81 void __iomem *membase; member
109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
123 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); in uniphier_fi2c_drain_rxfifo()
130 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); in uniphier_fi2c_set_irqs()
136 writel(mask, priv->membase + UNIPHIER_FI2C_IC); in uniphier_fi2c_clear_irqs()
144 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_stop()
154 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); in uniphier_fi2c_interrupt()
213 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_interrupt()
254 writel(0, priv->membase + UNIPHIER_FI2C_TBC); in uniphier_fi2c_tx_init()
257 priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_tx_init()
[all …]
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| /linux-6.6.21/drivers/clk/x86/ |
| D | clk-cgu.c | 30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
46 val = lgm_get_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_get_parent()
60 lgm_set_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_set_parent()
104 mux->membase = ctx->membase; in lgm_clk_register_mux()
117 lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val); in lgm_clk_register_mux()
128 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
157 lgm_set_clk_val(divider->membase, divider->reg, in lgm_clk_divider_set_rate()
168 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
217 div->membase = ctx->membase; in lgm_clk_register_divider()
233 lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); in lgm_clk_register_divider()
[all …]
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| /linux-6.6.21/drivers/input/keyboard/ |
| D | locomokbd.c | 72 static inline void locomokbd_charge_all(unsigned long membase) in locomokbd_charge_all() argument
74 locomo_writel(0x00FF, membase + LOCOMO_KSC); in locomokbd_charge_all()
77 static inline void locomokbd_activate_all(unsigned long membase) in locomokbd_activate_all() argument
81 locomo_writel(0, membase + LOCOMO_KSC); in locomokbd_activate_all()
82 r = locomo_readl(membase + LOCOMO_KIC); in locomokbd_activate_all()
84 locomo_writel(r, membase + LOCOMO_KIC); in locomokbd_activate_all()
87 static inline void locomokbd_activate_col(unsigned long membase, int col) in locomokbd_activate_col() argument
94 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_activate_col()
97 static inline void locomokbd_reset_col(unsigned long membase, int col) in locomokbd_reset_col() argument
102 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_reset_col()
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| /linux-6.6.21/drivers/dma/ |
| D | timb_dma.c | 72 void __iomem *membase; member
89 void __iomem *membase; member
118 ier = ioread32(td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
122 iowrite32(ier, td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
136 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id); in __td_dma_done_ack()
138 iowrite32(isr, td->membase + TIMBDMA_ISR); in __td_dma_done_ack()
193 td_chan, td_chan->chan.chan_id, td_chan->membase); in __td_start_dma()
198 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); in __td_start_dma()
199 iowrite32(td_desc->txd.phys, td_chan->membase + in __td_start_dma()
202 iowrite32(td_chan->bytes_per_line, td_chan->membase + in __td_start_dma()
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