| /linux-6.6.21/arch/arm/mm/ |
| D | proc-arm940.S | 39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
52 mcr p15, 0, ip, c7, c10, 4 @ drain WB
56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
112 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
162 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
[all …]
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| D | proc-mohawk.S | 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
[all …]
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| D | proc-arm946.S | 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | proc-arm1020.S | 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
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| D | proc-fa526.S | 39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-arm926.S | 53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-arm925.S | 84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
110 mcr p15, 0, ip, c7, c10, 4 @ drain WB
112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
131 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
133 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-arm920.S | 61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
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| D | proc-sa1100.S | 41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
74 mcr p15, 0, ip, c7, c10, 4 @ drain WB
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
[all …]
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| D | proc-v6.S | 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
63 mcr p15, 0, r1, c7, c5, 4 @ ISB
77 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
82 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
105 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
113 mcr p15, 0, r1, c13, c0, 1 @ set context ID
[all …]
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| D | proc-feroceon.S | 72 mcr p15, 1, r0, c15, c9, 0 @ clean L2
73 mcr p15, 0, r0, c7, c10, 4 @ drain WB
79 mcr p15, 0, r0, c1, c0, 0 @ disable caches
95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
96 mcr p15, 0, ip, c7, c10, 4 @ drain WB
98 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
116 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
127 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-arm922.S | 63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
80 mcr p15, 0, ip, c7, c10, 4 @ drain WB
82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
87 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
195 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
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| D | proc-arm1020e.S | 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
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| D | proc-xscale.S | 91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
118 mcr p15, 0, r1, c1, c0, 1
128 mcr p15, 0, r0, c1, c0, 0 @ disable caches
147 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
154 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
[all …]
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| D | cache-v6.S | 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
143 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
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| D | proc-xsc3.S | 68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
137 mcr p14, 0, r0, c7, c0, 0 @ go to idle
149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
[all …]
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| D | proc-arm1022.S | 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
213 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
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| D | proc-arm1026.S | 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
207 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
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| D | proc-sa110.S | 37 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
73 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
92 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
98 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
102 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
[all …]
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| D | cache-fa.S | 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
91 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
126 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
133 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
134 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
148 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-arm740.S | 40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
64 mcr p15, 0, r0, c6, c3 @ disable area 3~7
65 mcr p15, 0, r0, c6, c4
66 mcr p15, 0, r0, c6, c5
67 mcr p15, 0, r0, c6, c6
68 mcr p15, 0, r0, c6, c7
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
[all …]
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| D | tlb-v6.S | 39 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
57 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
70 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
85 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
86 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
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| D | cache-v4wb.S | 58 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
77 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
94 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
116 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
117 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
163 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
164 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
169 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
170 mcr p15, 0, r0, c7, c10, 4 @ drain WB
191 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| /linux-6.6.21/drivers/iio/adc/ |
| D | imx93_adc.c | 104 u32 mcr, msr; in imx93_adc_power_down() local
107 mcr = readl(adc->regs + IMX93_ADC_MCR); in imx93_adc_power_down()
108 mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); in imx93_adc_power_down()
109 writel(mcr, adc->regs + IMX93_ADC_MCR); in imx93_adc_power_down()
123 u32 mcr; in imx93_adc_power_up() local
126 mcr = readl(adc->regs + IMX93_ADC_MCR); in imx93_adc_power_up()
127 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); in imx93_adc_power_up()
128 writel(mcr, adc->regs + IMX93_ADC_MCR); in imx93_adc_power_up()
133 u32 mcr; in imx93_adc_config_ad_clk() local
139 mcr = readl(adc->regs + IMX93_ADC_MCR); in imx93_adc_config_ad_clk()
[all …]
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| /linux-6.6.21/drivers/w1/masters/ |
| D | sgi_w1.c | 23 u32 __iomem *mcr; member
28 static u8 sgi_w1_wait(u32 __iomem *mcr) in sgi_w1_wait() argument
33 mcr_val = readl(mcr); in sgi_w1_wait()
49 writel(MCR_PACK(520, 65), dev->mcr); in sgi_w1_reset_bus()
50 ret = sgi_w1_wait(dev->mcr); in sgi_w1_reset_bus()
66 writel(MCR_PACK(6, 13), dev->mcr); in sgi_w1_touch_bit()
68 writel(MCR_PACK(80, 30), dev->mcr); in sgi_w1_touch_bit()
70 ret = sgi_w1_wait(dev->mcr); in sgi_w1_touch_bit()
86 sdev->mcr = devm_platform_ioremap_resource(pdev, 0); in sgi_w1_probe()
87 if (IS_ERR(sdev->mcr)) in sgi_w1_probe()
[all …]
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