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Searched refs:mc_writel (Results 1 – 6 of 6) sorted by relevance

/linux-6.6.21/drivers/memory/tegra/
Dtegra20.c288 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
304 mc_writel(mc, value | BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_deassert()
320 mc_writel(mc, value, rst->control); in tegra20_mc_block_dma()
348 mc_writel(mc, value, rst->control); in tegra20_mc_unblock_dma()
461 mc_writel(mc, 0x00000000, MC_STAT_CONTROL); in tegra20_mc_stat_gather()
462 mc_writel(mc, control_0, MC_STAT_EMC_CONTROL_0); in tegra20_mc_stat_gather()
463 mc_writel(mc, control_1, MC_STAT_EMC_CONTROL_1); in tegra20_mc_stat_gather()
464 mc_writel(mc, 0xffffffff, MC_STAT_EMC_CLOCK_LIMIT); in tegra20_mc_stat_gather()
466 mc_writel(mc, EMC_GATHER_ENABLE, MC_STAT_CONTROL); in tegra20_mc_stat_gather()
468 mc_writel(mc, EMC_GATHER_DISABLE, MC_STAT_CONTROL); in tegra20_mc_stat_gather()
[all …]
Dmc.c145 mc_writel(mc, value, rst->control); in tegra_mc_block_dma_common()
167 mc_writel(mc, value, rst->control); in tegra_mc_unblock_dma_common()
363 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); in tegra_mc_write_emem_configuration()
399 mc_writel(mc, value, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
409 mc_writel(mc, value, client->regs.la.reg); in tegra_mc_setup_latency_allowance()
413 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in tegra_mc_setup_latency_allowance()
520 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); in tegra30_mc_probe()
730 mc_writel(mc, status, MC_INTSTATUS); in tegra30_mc_handle_irq()
951 mc_writel(mc, mc->soc->intmask, MC_INTMASK); in tegra_mc_probe()
Dmc.h141 static inline void mc_writel(const struct tegra_mc *mc, u32 value, in mc_writel() function
Dtegra30-emc.c591 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
592 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in emc_prepare_timing_change()
596 mc_writel(emc->mc, in emc_prepare_timing_change()
838 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE); in emc_complete_timing_change()
Dtegra210-emc-cc-r21021.c1216 mc_writel(emc->mc, values[i], offsets[i]); in tegra210_emc_r21021_set_clock()
1228 mc_writel(emc->mc, next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
1666 mc_writel(emc->mc, next->la_scale_regs[i], in tegra210_emc_r21021_set_clock()
Dtegra30.c1288 mc_writel(mc, value, client->regs.la.reg); in tegra30_mc_tune_client_latency()