Searched refs:max_tile_pipes (Results 1 – 20 of 20) sorted by relevance
378 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()380 *value = rdev->config.si.max_tile_pipes; in radeon_info_ioctl()382 *value = rdev->config.cayman.max_tile_pipes; in radeon_info_ioctl()384 *value = rdev->config.evergreen.max_tile_pipes; in radeon_info_ioctl()386 *value = rdev->config.rv770.max_tile_pipes; in radeon_info_ioctl()388 *value = rdev->config.r600.max_tile_pipes; in radeon_info_ioctl()
1195 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()1215 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1239 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()1259 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1321 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()1336 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
3161 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3183 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3205 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3228 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3250 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3272 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3300 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3322 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3344 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3366 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()[all …]
2012 unsigned max_tile_pipes; member2034 unsigned max_tile_pipes; member2061 unsigned max_tile_pipes; member2088 unsigned max_tile_pipes; member2126 unsigned max_tile_pipes; member2157 unsigned max_tile_pipes; member
2008 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()2024 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()2042 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()2057 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()2088 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()2104 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
3100 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()3117 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()3135 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3152 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3169 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3206 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
895 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()919 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
2346 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3179 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3196 rdev->config.cik.max_tile_pipes = 16; in cik_gpu_init()3213 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3232 rdev->config.cik.max_tile_pipes = 2; in cik_gpu_init()3267 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; in cik_gpu_init()
1573 adev->gfx.config.max_tile_pipes = 12; in gfx_v6_0_constants_init()1590 adev->gfx.config.max_tile_pipes = 8; in gfx_v6_0_constants_init()1607 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1624 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1641 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1670 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
189 unsigned max_tile_pipes; member
4218 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4235 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()4252 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4271 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()4296 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
726 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; in amdgpu_atombios_get_gfx_info()
1663 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1680 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()1727 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()1744 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1761 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1778 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()1803 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
889 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
707 adev->gfx.config.max_tile_pipes = in gfx_v9_4_3_gpu_early_init()
4230 adev->gfx.config.max_tile_pipes = in get_gb_addr_config()
1933 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
4404 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
1714 uint8_t max_tile_pipes; member1734 uint8_t max_tile_pipes; member1835 uint8_t max_tile_pipes; member
5653 UCHAR max_tile_pipes; member5666 UCHAR max_tile_pipes; member