1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
6 
7 /* This header file defines the Admin Queue commands, error codes and
8  * descriptor format. It is shared between Firmware and Software.
9  */
10 
11 #define ICE_MAX_VSI			768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM	0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX	9728
14 
15 struct ice_aqc_generic {
16 	__le32 param0;
17 	__le32 param1;
18 	__le32 addr_high;
19 	__le32 addr_low;
20 };
21 
22 /* Get version (direct 0x0001) */
23 struct ice_aqc_get_ver {
24 	__le32 rom_ver;
25 	__le32 fw_build;
26 	u8 fw_branch;
27 	u8 fw_major;
28 	u8 fw_minor;
29 	u8 fw_patch;
30 	u8 api_branch;
31 	u8 api_major;
32 	u8 api_minor;
33 	u8 api_patch;
34 };
35 
36 /* Send driver version (indirect 0x0002) */
37 struct ice_aqc_driver_ver {
38 	u8 major_ver;
39 	u8 minor_ver;
40 	u8 build_ver;
41 	u8 subbuild_ver;
42 	u8 reserved[4];
43 	__le32 addr_high;
44 	__le32 addr_low;
45 };
46 
47 /* Queue Shutdown (direct 0x0003) */
48 struct ice_aqc_q_shutdown {
49 	u8 driver_unloading;
50 #define ICE_AQC_DRIVER_UNLOADING	BIT(0)
51 	u8 reserved[15];
52 };
53 
54 /* Request resource ownership (direct 0x0008)
55  * Release resource ownership (direct 0x0009)
56  */
57 struct ice_aqc_req_res {
58 	__le16 res_id;
59 #define ICE_AQC_RES_ID_NVM		1
60 #define ICE_AQC_RES_ID_SDP		2
61 #define ICE_AQC_RES_ID_CHNG_LOCK	3
62 #define ICE_AQC_RES_ID_GLBL_LOCK	4
63 	__le16 access_type;
64 #define ICE_AQC_RES_ACCESS_READ		1
65 #define ICE_AQC_RES_ACCESS_WRITE	2
66 
67 	/* Upon successful completion, FW writes this value and driver is
68 	 * expected to release resource before timeout. This value is provided
69 	 * in milliseconds.
70 	 */
71 	__le32 timeout;
72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS	3000
73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS	180000
74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS	1000
75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS	3000
76 	/* For SDP: pin ID of the SDP */
77 	__le32 res_number;
78 	/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
79 	__le16 status;
80 #define ICE_AQ_RES_GLBL_SUCCESS		0
81 #define ICE_AQ_RES_GLBL_IN_PROG		1
82 #define ICE_AQ_RES_GLBL_DONE		2
83 	u8 reserved[2];
84 };
85 
86 /* Get function capabilities (indirect 0x000A)
87  * Get device capabilities (indirect 0x000B)
88  */
89 struct ice_aqc_list_caps {
90 	u8 cmd_flags;
91 	u8 pf_index;
92 	u8 reserved[2];
93 	__le32 count;
94 	__le32 addr_high;
95 	__le32 addr_low;
96 };
97 
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
100 	__le16 cap;
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS			0x0005
102 #define ICE_AQC_CAPS_SRIOV				0x0012
103 #define ICE_AQC_CAPS_VF					0x0013
104 #define ICE_AQC_CAPS_VSI				0x0017
105 #define ICE_AQC_CAPS_DCB				0x0018
106 #define ICE_AQC_CAPS_RSS				0x0040
107 #define ICE_AQC_CAPS_RXQS				0x0041
108 #define ICE_AQC_CAPS_TXQS				0x0042
109 #define ICE_AQC_CAPS_MSIX				0x0043
110 #define ICE_AQC_CAPS_FD					0x0045
111 #define ICE_AQC_CAPS_1588				0x0046
112 #define ICE_AQC_CAPS_MAX_MTU				0x0047
113 #define ICE_AQC_CAPS_NVM_VER				0x0048
114 #define ICE_AQC_CAPS_PENDING_NVM_VER			0x0049
115 #define ICE_AQC_CAPS_OROM_VER				0x004A
116 #define ICE_AQC_CAPS_PENDING_OROM_VER			0x004B
117 #define ICE_AQC_CAPS_NET_VER				0x004C
118 #define ICE_AQC_CAPS_PENDING_NET_VER			0x004D
119 #define ICE_AQC_CAPS_RDMA				0x0051
120 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE		0x0076
121 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT		0x0077
122 #define ICE_AQC_CAPS_NVM_MGMT				0x0080
123 #define ICE_AQC_CAPS_FW_LAG_SUPPORT			0x0092
124 #define ICE_AQC_BIT_ROCEV2_LAG				0x01
125 #define ICE_AQC_BIT_SRIOV_LAG				0x02
126 
127 	u8 major_ver;
128 	u8 minor_ver;
129 	/* Number of resources described by this capability */
130 	__le32 number;
131 	/* Only meaningful for some types of resources */
132 	__le32 logical_id;
133 	/* Only meaningful for some types of resources */
134 	__le32 phys_id;
135 	__le64 rsvd1;
136 	__le64 rsvd2;
137 };
138 
139 /* Manage MAC address, read command - indirect (0x0107)
140  * This struct is also used for the response
141  */
142 struct ice_aqc_manage_mac_read {
143 	__le16 flags; /* Zeroed by device driver */
144 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID		BIT(4)
145 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID		BIT(5)
146 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID		BIT(6)
147 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID		BIT(7)
148 #define ICE_AQC_MAN_MAC_READ_S			4
149 #define ICE_AQC_MAN_MAC_READ_M			(0xF << ICE_AQC_MAN_MAC_READ_S)
150 	u8 rsvd[2];
151 	u8 num_addr; /* Used in response */
152 	u8 rsvd1[3];
153 	__le32 addr_high;
154 	__le32 addr_low;
155 };
156 
157 /* Response buffer format for manage MAC read command */
158 struct ice_aqc_manage_mac_read_resp {
159 	u8 lport_num;
160 	u8 addr_type;
161 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN		0
162 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL		1
163 	u8 mac_addr[ETH_ALEN];
164 };
165 
166 /* Manage MAC address, write command - direct (0x0108) */
167 struct ice_aqc_manage_mac_write {
168 	u8 rsvd;
169 	u8 flags;
170 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN		BIT(0)
171 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP	BIT(1)
172 #define ICE_AQC_MAN_MAC_WR_S		6
173 #define ICE_AQC_MAN_MAC_WR_M		ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
174 #define ICE_AQC_MAN_MAC_UPDATE_LAA	0
175 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL	BIT(ICE_AQC_MAN_MAC_WR_S)
176 	/* byte stream in network order */
177 	u8 mac_addr[ETH_ALEN];
178 	__le32 addr_high;
179 	__le32 addr_low;
180 };
181 
182 /* Clear PXE Command and response (direct 0x0110) */
183 struct ice_aqc_clear_pxe {
184 	u8 rx_cnt;
185 #define ICE_AQC_CLEAR_PXE_RX_CNT		0x2
186 	u8 reserved[15];
187 };
188 
189 /* Get switch configuration (0x0200) */
190 struct ice_aqc_get_sw_cfg {
191 	/* Reserved for command and copy of request flags for response */
192 	__le16 flags;
193 	/* First desc in case of command and next_elem in case of response
194 	 * In case of response, if it is not zero, means all the configuration
195 	 * was not returned and new command shall be sent with this value in
196 	 * the 'first desc' field
197 	 */
198 	__le16 element;
199 	/* Reserved for command, only used for response */
200 	__le16 num_elems;
201 	__le16 rsvd;
202 	__le32 addr_high;
203 	__le32 addr_low;
204 };
205 
206 /* Each entry in the response buffer is of the following type: */
207 struct ice_aqc_get_sw_cfg_resp_elem {
208 	/* VSI/Port Number */
209 	__le16 vsi_port_num;
210 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S	0
211 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M	\
212 			(0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
213 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S	14
214 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M	(0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
215 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT	0
216 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT	1
217 #define ICE_AQC_GET_SW_CONF_RESP_VSI		2
218 
219 	/* SWID VSI/Port belongs to */
220 	__le16 swid;
221 
222 	/* Bit 14..0 : PF/VF number VSI belongs to
223 	 * Bit 15 : VF indication bit
224 	 */
225 	__le16 pf_vf_num;
226 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S	0
227 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M	\
228 				(0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
229 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF		BIT(15)
230 };
231 
232 /* Set Port parameters, (direct, 0x0203) */
233 struct ice_aqc_set_port_params {
234 	__le16 cmd_flags;
235 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA	BIT(2)
236 	__le16 bad_frame_vsi;
237 	__le16 swid;
238 #define ICE_AQC_PORT_SWID_VALID			BIT(15)
239 #define ICE_AQC_PORT_SWID_M			0xFF
240 	u8 reserved[10];
241 };
242 
243 /* These resource type defines are used for all switch resource
244  * commands where a resource type is required, such as:
245  * Get Resource Allocation command (indirect 0x0204)
246  * Allocate Resources command (indirect 0x0208)
247  * Free Resources command (indirect 0x0209)
248  * Get Allocated Resource Descriptors Command (indirect 0x020A)
249  * Share Resource command (indirect 0x020B)
250  */
251 #define ICE_AQC_RES_TYPE_VSI_LIST_REP			0x03
252 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE			0x04
253 #define ICE_AQC_RES_TYPE_RECIPE				0x05
254 #define ICE_AQC_RES_TYPE_SWID				0x07
255 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK		0x21
256 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES	0x22
257 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES		0x23
258 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID		0x58
259 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM		0x59
260 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID		0x60
261 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM		0x61
262 
263 #define ICE_AQC_RES_TYPE_FLAG_SHARED			BIT(7)
264 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM		BIT(12)
265 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX		BIT(13)
266 
267 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED			0x00
268 
269 #define ICE_AQC_RES_TYPE_S	0
270 #define ICE_AQC_RES_TYPE_M	(0x07F << ICE_AQC_RES_TYPE_S)
271 
272 /* Allocate Resources command (indirect 0x0208)
273  * Free Resources command (indirect 0x0209)
274  * Share Resource command (indirect 0x020B)
275  */
276 struct ice_aqc_alloc_free_res_cmd {
277 	__le16 num_entries; /* Number of Resource entries */
278 	u8 reserved[6];
279 	__le32 addr_high;
280 	__le32 addr_low;
281 };
282 
283 /* Resource descriptor */
284 struct ice_aqc_res_elem {
285 	union {
286 		__le16 sw_resp;
287 		__le16 flu_resp;
288 	} e;
289 };
290 
291 /* Buffer for Allocate/Free Resources commands */
292 struct ice_aqc_alloc_free_res_elem {
293 	__le16 res_type; /* Types defined above cmd 0x0204 */
294 #define ICE_AQC_RES_TYPE_SHARED_S	7
295 #define ICE_AQC_RES_TYPE_SHARED_M	(0x1 << ICE_AQC_RES_TYPE_SHARED_S)
296 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S	8
297 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M	\
298 				(0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
299 	__le16 num_elems;
300 	struct ice_aqc_res_elem elem[];
301 };
302 
303 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
304 struct ice_aqc_set_vlan_mode {
305 	u8 reserved;
306 	u8 l2tag_prio_tagging;
307 #define ICE_AQ_VLAN_PRIO_TAG_S			0
308 #define ICE_AQ_VLAN_PRIO_TAG_M			(0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
309 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED	0x0
310 #define ICE_AQ_VLAN_PRIO_TAG_STAG		0x1
311 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG		0x2
312 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN		0x3
313 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG		0x4
314 #define ICE_AQ_VLAN_PRIO_TAG_MAX		0x4
315 #define ICE_AQ_VLAN_PRIO_TAG_ERROR		0x7
316 	u8 l2tag_reserved[64];
317 	u8 rdma_packet;
318 #define ICE_AQ_VLAN_RDMA_TAG_S			0
319 #define ICE_AQ_VLAN_RDMA_TAG_M			(0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
320 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING	0x10
321 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING	0x1A
322 	u8 rdma_reserved[2];
323 	u8 mng_vlan_prot_id;
324 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER	0x10
325 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER	0x11
326 	u8 prot_id_reserved[30];
327 };
328 
329 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
330 struct ice_aqc_get_vlan_mode {
331 	u8 vlan_mode;
332 #define ICE_AQ_VLAN_MODE_DVM_ENA	BIT(0)
333 	u8 l2tag_prio_tagging;
334 	u8 reserved[98];
335 };
336 
337 /* Add VSI (indirect 0x0210)
338  * Update VSI (indirect 0x0211)
339  * Get VSI (indirect 0x0212)
340  * Free VSI (indirect 0x0213)
341  */
342 struct ice_aqc_add_get_update_free_vsi {
343 	__le16 vsi_num;
344 #define ICE_AQ_VSI_NUM_S	0
345 #define ICE_AQ_VSI_NUM_M	(0x03FF << ICE_AQ_VSI_NUM_S)
346 #define ICE_AQ_VSI_IS_VALID	BIT(15)
347 	__le16 cmd_flags;
348 #define ICE_AQ_VSI_KEEP_ALLOC	0x1
349 	u8 vf_id;
350 	u8 reserved;
351 	__le16 vsi_flags;
352 #define ICE_AQ_VSI_TYPE_S	0
353 #define ICE_AQ_VSI_TYPE_M	(0x3 << ICE_AQ_VSI_TYPE_S)
354 #define ICE_AQ_VSI_TYPE_VF	0x0
355 #define ICE_AQ_VSI_TYPE_VMDQ2	0x1
356 #define ICE_AQ_VSI_TYPE_PF	0x2
357 #define ICE_AQ_VSI_TYPE_EMP_MNG	0x3
358 	__le32 addr_high;
359 	__le32 addr_low;
360 };
361 
362 /* Response descriptor for:
363  * Add VSI (indirect 0x0210)
364  * Update VSI (indirect 0x0211)
365  * Free VSI (indirect 0x0213)
366  */
367 struct ice_aqc_add_update_free_vsi_resp {
368 	__le16 vsi_num;
369 	__le16 ext_status;
370 	__le16 vsi_used;
371 	__le16 vsi_free;
372 	__le32 addr_high;
373 	__le32 addr_low;
374 };
375 
376 struct ice_aqc_vsi_props {
377 	__le16 valid_sections;
378 #define ICE_AQ_VSI_PROP_SW_VALID		BIT(0)
379 #define ICE_AQ_VSI_PROP_SECURITY_VALID		BIT(1)
380 #define ICE_AQ_VSI_PROP_VLAN_VALID		BIT(2)
381 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID		BIT(3)
382 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID	BIT(4)
383 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID		BIT(5)
384 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID		BIT(6)
385 #define ICE_AQ_VSI_PROP_Q_OPT_VALID		BIT(7)
386 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID		BIT(8)
387 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID		BIT(11)
388 #define ICE_AQ_VSI_PROP_PASID_VALID		BIT(12)
389 	/* switch section */
390 	u8 sw_id;
391 	u8 sw_flags;
392 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB		BIT(5)
393 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB		BIT(6)
394 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE		BIT(7)
395 	u8 sw_flags2;
396 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S	0
397 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
398 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA	BIT(0)
399 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA		BIT(4)
400 	u8 veb_stat_id;
401 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S		0
402 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M		(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
403 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID		BIT(5)
404 	/* security section */
405 	u8 sec_flags;
406 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	BIT(0)
407 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF	BIT(2)
408 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S		4
409 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M		(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
410 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA	BIT(0)
411 	u8 sec_reserved;
412 	/* VLAN section */
413 	__le16 port_based_inner_vlan; /* VLANS include priority bits */
414 	u8 inner_vlan_reserved[2];
415 	u8 inner_vlan_flags;
416 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S		0
417 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M		(0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
418 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED	0x1
419 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED	0x2
420 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL	0x3
421 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID	BIT(2)
422 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S		3
423 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M		(0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
424 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH	0x0U
425 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP	0x1U
426 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR		0x2U
427 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING	0x3U
428 	u8 inner_vlan_reserved2[3];
429 	/* ingress egress up sections */
430 	__le32 ingress_table; /* bitmap, 3 bits per up */
431 #define ICE_AQ_VSI_UP_TABLE_UP0_S		0
432 #define ICE_AQ_VSI_UP_TABLE_UP0_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
433 #define ICE_AQ_VSI_UP_TABLE_UP1_S		3
434 #define ICE_AQ_VSI_UP_TABLE_UP1_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
435 #define ICE_AQ_VSI_UP_TABLE_UP2_S		6
436 #define ICE_AQ_VSI_UP_TABLE_UP2_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
437 #define ICE_AQ_VSI_UP_TABLE_UP3_S		9
438 #define ICE_AQ_VSI_UP_TABLE_UP3_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
439 #define ICE_AQ_VSI_UP_TABLE_UP4_S		12
440 #define ICE_AQ_VSI_UP_TABLE_UP4_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
441 #define ICE_AQ_VSI_UP_TABLE_UP5_S		15
442 #define ICE_AQ_VSI_UP_TABLE_UP5_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
443 #define ICE_AQ_VSI_UP_TABLE_UP6_S		18
444 #define ICE_AQ_VSI_UP_TABLE_UP6_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
445 #define ICE_AQ_VSI_UP_TABLE_UP7_S		21
446 #define ICE_AQ_VSI_UP_TABLE_UP7_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
447 	__le32 egress_table;   /* same defines as for ingress table */
448 	/* outer tags section */
449 	__le16 port_based_outer_vlan;
450 	u8 outer_vlan_flags;
451 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S		0
452 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M		(0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
453 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH	0x0
454 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP	0x1
455 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW	0x2
456 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING	0x3
457 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S		2
458 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M		(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
459 #define ICE_AQ_VSI_OUTER_TAG_NONE		0x0
460 #define ICE_AQ_VSI_OUTER_TAG_STAG		0x1
461 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100		0x2
462 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100		0x3
463 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT		BIT(4)
464 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S			5
465 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M			(0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
466 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED	0x1
467 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED	0x2
468 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL		0x3
469 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC		BIT(7)
470 	u8 outer_vlan_reserved;
471 	/* queue mapping section */
472 	__le16 mapping_flags;
473 #define ICE_AQ_VSI_Q_MAP_CONTIG			0x0
474 #define ICE_AQ_VSI_Q_MAP_NONCONTIG		BIT(0)
475 	__le16 q_mapping[16];
476 #define ICE_AQ_VSI_Q_S				0
477 #define ICE_AQ_VSI_Q_M				(0x7FF << ICE_AQ_VSI_Q_S)
478 	__le16 tc_mapping[8];
479 #define ICE_AQ_VSI_TC_Q_OFFSET_S		0
480 #define ICE_AQ_VSI_TC_Q_OFFSET_M		(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
481 #define ICE_AQ_VSI_TC_Q_NUM_S			11
482 #define ICE_AQ_VSI_TC_Q_NUM_M			(0xF << ICE_AQ_VSI_TC_Q_NUM_S)
483 	/* queueing option section */
484 	u8 q_opt_rss;
485 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S		0
486 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M		(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
487 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI		0x0
488 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF		0x2
489 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL		0x3
490 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S		2
491 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M		(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
492 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S		6
493 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M		GENMASK(7, 6)
494 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ		0x0U
495 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ	0x1U
496 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR		0x2U
497 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH		0x3U
498 	u8 q_opt_tc;
499 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S		0
500 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M		(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
501 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR		BIT(7)
502 	u8 q_opt_flags;
503 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN		BIT(0)
504 	u8 q_opt_reserved[3];
505 	/* outer up section */
506 	__le32 outer_up_table; /* same structure and defines as ingress tbl */
507 	/* section 10 */
508 	__le16 sect_10_reserved;
509 	/* flow director section */
510 	__le16 fd_options;
511 #define ICE_AQ_VSI_FD_ENABLE			BIT(0)
512 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE		BIT(1)
513 #define ICE_AQ_VSI_FD_PROG_ENABLE		BIT(3)
514 	__le16 max_fd_fltr_dedicated;
515 	__le16 max_fd_fltr_shared;
516 	__le16 fd_def_q;
517 #define ICE_AQ_VSI_FD_DEF_Q_S			0
518 #define ICE_AQ_VSI_FD_DEF_Q_M			(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
519 #define ICE_AQ_VSI_FD_DEF_GRP_S			12
520 #define ICE_AQ_VSI_FD_DEF_GRP_M			(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
521 	__le16 fd_report_opt;
522 #define ICE_AQ_VSI_FD_REPORT_Q_S		0
523 #define ICE_AQ_VSI_FD_REPORT_Q_M		(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
524 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S		12
525 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M		(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
526 #define ICE_AQ_VSI_FD_DEF_DROP			BIT(15)
527 	/* PASID section */
528 	__le32 pasid_id;
529 #define ICE_AQ_VSI_PASID_ID_S			0
530 #define ICE_AQ_VSI_PASID_ID_M			(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
531 #define ICE_AQ_VSI_PASID_ID_VALID		BIT(31)
532 	u8 reserved[24];
533 };
534 
535 #define ICE_MAX_NUM_RECIPES 64
536 
537 /* Add/Get Recipe (indirect 0x0290/0x0292) */
538 struct ice_aqc_add_get_recipe {
539 	__le16 num_sub_recipes;	/* Input in Add cmd, Output in Get cmd */
540 	__le16 return_index;	/* Input, used for Get cmd only */
541 	u8 reserved[4];
542 	__le32 addr_high;
543 	__le32 addr_low;
544 };
545 
546 struct ice_aqc_recipe_content {
547 	u8 rid;
548 #define ICE_AQ_RECIPE_ID_S		0
549 #define ICE_AQ_RECIPE_ID_M		(0x3F << ICE_AQ_RECIPE_ID_S)
550 #define ICE_AQ_RECIPE_ID_IS_ROOT	BIT(7)
551 #define ICE_AQ_SW_ID_LKUP_IDX		0
552 	u8 lkup_indx[5];
553 #define ICE_AQ_RECIPE_LKUP_DATA_S	0
554 #define ICE_AQ_RECIPE_LKUP_DATA_M	(0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
555 #define ICE_AQ_RECIPE_LKUP_IGNORE	BIT(7)
556 #define ICE_AQ_SW_ID_LKUP_MASK		0x00FF
557 	__le16 mask[5];
558 	u8 result_indx;
559 #define ICE_AQ_RECIPE_RESULT_DATA_S	0
560 #define ICE_AQ_RECIPE_RESULT_DATA_M	(0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
561 #define ICE_AQ_RECIPE_RESULT_EN		BIT(7)
562 	u8 rsvd0[3];
563 	u8 act_ctrl_join_priority;
564 	u8 act_ctrl_fwd_priority;
565 #define ICE_AQ_RECIPE_FWD_PRIORITY_S	0
566 #define ICE_AQ_RECIPE_FWD_PRIORITY_M	(0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
567 	u8 act_ctrl;
568 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2	BIT(0)
569 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2	BIT(1)
570 #define ICE_AQ_RECIPE_ACT_INV_ACT	BIT(2)
571 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S	4
572 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M	(0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
573 	u8 rsvd1;
574 	__le32 dflt_act;
575 #define ICE_AQ_RECIPE_DFLT_ACT_S	0
576 #define ICE_AQ_RECIPE_DFLT_ACT_M	(0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
577 #define ICE_AQ_RECIPE_DFLT_ACT_VALID	BIT(31)
578 };
579 
580 struct ice_aqc_recipe_data_elem {
581 	u8 recipe_indx;
582 	u8 resp_bits;
583 #define ICE_AQ_RECIPE_WAS_UPDATED	BIT(0)
584 	u8 rsvd0[2];
585 	u8 recipe_bitmap[8];
586 	u8 rsvd1[4];
587 	struct ice_aqc_recipe_content content;
588 	u8 rsvd2[20];
589 };
590 
591 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
592 struct ice_aqc_recipe_to_profile {
593 	__le16 profile_id;
594 	u8 rsvd[6];
595 	DECLARE_BITMAP(recipe_assoc, ICE_MAX_NUM_RECIPES);
596 };
597 
598 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
599  */
600 struct ice_aqc_sw_rules {
601 	/* ops: add switch rules, referring the number of rules.
602 	 * ops: update switch rules, referring the number of filters
603 	 * ops: remove switch rules, referring the entry index.
604 	 * ops: get switch rules, referring to the number of filters.
605 	 */
606 	__le16 num_rules_fltr_entry_index;
607 	u8 reserved[6];
608 	__le32 addr_high;
609 	__le32 addr_low;
610 };
611 
612 /* Add switch rule response:
613  * Content of return buffer is same as the input buffer. The status field and
614  * LUT index are updated as part of the response
615  */
616 struct ice_aqc_sw_rules_elem_hdr {
617 	__le16 type; /* Switch rule type, one of T_... */
618 #define ICE_AQC_SW_RULES_T_LKUP_RX		0x0
619 #define ICE_AQC_SW_RULES_T_LKUP_TX		0x1
620 #define ICE_AQC_SW_RULES_T_LG_ACT		0x2
621 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET		0x3
622 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR	0x4
623 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET	0x5
624 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR	0x6
625 	__le16 status;
626 } __packed __aligned(sizeof(__le16));
627 
628 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
629  * This structures describes the lookup rules and associated actions. "index"
630  * is returned as part of a response to a successful Add command, and can be
631  * used to identify the rule for Update/Get/Remove commands.
632  */
633 struct ice_sw_rule_lkup_rx_tx {
634 	struct ice_aqc_sw_rules_elem_hdr hdr;
635 
636 	__le16 recipe_id;
637 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD		10
638 	/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
639 	__le16 src;
640 	__le32 act;
641 
642 	/* Bit 0:1 - Action type */
643 #define ICE_SINGLE_ACT_TYPE_S	0x00
644 #define ICE_SINGLE_ACT_TYPE_M	(0x3 << ICE_SINGLE_ACT_TYPE_S)
645 
646 	/* Bit 2 - Loop back enable
647 	 * Bit 3 - LAN enable
648 	 */
649 #define ICE_SINGLE_ACT_LB_ENABLE	BIT(2)
650 #define ICE_SINGLE_ACT_LAN_ENABLE	BIT(3)
651 
652 	/* Action type = 0 - Forward to VSI or VSI list */
653 #define ICE_SINGLE_ACT_VSI_FORWARDING	0x0
654 
655 #define ICE_SINGLE_ACT_VSI_ID_S		4
656 #define ICE_SINGLE_ACT_VSI_ID_M		(0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
657 #define ICE_SINGLE_ACT_VSI_LIST_ID_S	4
658 #define ICE_SINGLE_ACT_VSI_LIST_ID_M	(0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
659 	/* This bit needs to be set if action is forward to VSI list */
660 #define ICE_SINGLE_ACT_VSI_LIST		BIT(14)
661 #define ICE_SINGLE_ACT_VALID_BIT	BIT(17)
662 #define ICE_SINGLE_ACT_DROP		BIT(18)
663 
664 	/* Action type = 1 - Forward to Queue of Queue group */
665 #define ICE_SINGLE_ACT_TO_Q		0x1
666 #define ICE_SINGLE_ACT_Q_INDEX_S	4
667 #define ICE_SINGLE_ACT_Q_INDEX_M	(0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
668 #define ICE_SINGLE_ACT_Q_REGION_S	15
669 #define ICE_SINGLE_ACT_Q_REGION_M	(0x7 << ICE_SINGLE_ACT_Q_REGION_S)
670 #define ICE_SINGLE_ACT_Q_PRIORITY	BIT(18)
671 
672 	/* Action type = 2 - Prune */
673 #define ICE_SINGLE_ACT_PRUNE		0x2
674 #define ICE_SINGLE_ACT_EGRESS		BIT(15)
675 #define ICE_SINGLE_ACT_INGRESS		BIT(16)
676 #define ICE_SINGLE_ACT_PRUNET		BIT(17)
677 	/* Bit 18 should be set to 0 for this action */
678 
679 	/* Action type = 2 - Pointer */
680 #define ICE_SINGLE_ACT_PTR		0x2
681 #define ICE_SINGLE_ACT_PTR_VAL_S	4
682 #define ICE_SINGLE_ACT_PTR_VAL_M	(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
683 	/* Bit 18 should be set to 1 */
684 #define ICE_SINGLE_ACT_PTR_BIT		BIT(18)
685 
686 	/* Action type = 3 - Other actions. Last two bits
687 	 * are other action identifier
688 	 */
689 #define ICE_SINGLE_ACT_OTHER_ACTS		0x3
690 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S	17
691 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M	\
692 				(0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
693 
694 	/* Bit 17:18 - Defines other actions */
695 	/* Other action = 0 - Mirror VSI */
696 #define ICE_SINGLE_OTHER_ACT_MIRROR		0
697 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S	4
698 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M	\
699 				(0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
700 
701 	/* Other action = 3 - Set Stat count */
702 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT		3
703 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S	4
704 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M	\
705 				(0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
706 
707 	__le16 index; /* The index of the rule in the lookup table */
708 	/* Length and values of the header to be matched per recipe or
709 	 * lookup-type
710 	 */
711 	__le16 hdr_len;
712 	u8 hdr_data[];
713 } __packed __aligned(sizeof(__le16));
714 
715 /* Add/Update/Remove large action command/response entry
716  * "index" is returned as part of a response to a successful Add command, and
717  * can be used to identify the action for Update/Get/Remove commands.
718  */
719 struct ice_sw_rule_lg_act {
720 	struct ice_aqc_sw_rules_elem_hdr hdr;
721 
722 	__le16 index; /* Index in large action table */
723 	__le16 size;
724 	/* Max number of large actions */
725 #define ICE_MAX_LG_ACT	4
726 	/* Bit 0:1 - Action type */
727 #define ICE_LG_ACT_TYPE_S	0
728 #define ICE_LG_ACT_TYPE_M	(0x7 << ICE_LG_ACT_TYPE_S)
729 
730 	/* Action type = 0 - Forward to VSI or VSI list */
731 #define ICE_LG_ACT_VSI_FORWARDING	0
732 #define ICE_LG_ACT_VSI_ID_S		3
733 #define ICE_LG_ACT_VSI_ID_M		(0x3FF << ICE_LG_ACT_VSI_ID_S)
734 #define ICE_LG_ACT_VSI_LIST_ID_S	3
735 #define ICE_LG_ACT_VSI_LIST_ID_M	(0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
736 	/* This bit needs to be set if action is forward to VSI list */
737 #define ICE_LG_ACT_VSI_LIST		BIT(13)
738 
739 #define ICE_LG_ACT_VALID_BIT		BIT(16)
740 
741 	/* Action type = 1 - Forward to Queue of Queue group */
742 #define ICE_LG_ACT_TO_Q			0x1
743 #define ICE_LG_ACT_Q_INDEX_S		3
744 #define ICE_LG_ACT_Q_INDEX_M		(0x7FF << ICE_LG_ACT_Q_INDEX_S)
745 #define ICE_LG_ACT_Q_REGION_S		14
746 #define ICE_LG_ACT_Q_REGION_M		(0x7 << ICE_LG_ACT_Q_REGION_S)
747 #define ICE_LG_ACT_Q_PRIORITY_SET	BIT(17)
748 
749 	/* Action type = 2 - Prune */
750 #define ICE_LG_ACT_PRUNE		0x2
751 #define ICE_LG_ACT_EGRESS		BIT(14)
752 #define ICE_LG_ACT_INGRESS		BIT(15)
753 #define ICE_LG_ACT_PRUNET		BIT(16)
754 
755 	/* Action type = 3 - Mirror VSI */
756 #define ICE_LG_OTHER_ACT_MIRROR		0x3
757 #define ICE_LG_ACT_MIRROR_VSI_ID_S	3
758 #define ICE_LG_ACT_MIRROR_VSI_ID_M	(0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
759 
760 	/* Action type = 5 - Generic Value */
761 #define ICE_LG_ACT_GENERIC		0x5
762 #define ICE_LG_ACT_GENERIC_VALUE_S	3
763 #define ICE_LG_ACT_GENERIC_VALUE_M	(0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
764 #define ICE_LG_ACT_GENERIC_OFFSET_S	19
765 #define ICE_LG_ACT_GENERIC_OFFSET_M	(0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
766 #define ICE_LG_ACT_GENERIC_PRIORITY_S	22
767 #define ICE_LG_ACT_GENERIC_PRIORITY_M	(0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
768 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX	7
769 
770 	/* Action = 7 - Set Stat count */
771 #define ICE_LG_ACT_STAT_COUNT		0x7
772 #define ICE_LG_ACT_STAT_COUNT_S		3
773 #define ICE_LG_ACT_STAT_COUNT_M		(0x7F << ICE_LG_ACT_STAT_COUNT_S)
774 	__le32 act[]; /* array of size for actions */
775 } __packed __aligned(sizeof(__le16));
776 
777 /* Add/Update/Remove VSI list command/response entry
778  * "index" is returned as part of a response to a successful Add command, and
779  * can be used to identify the VSI list for Update/Get/Remove commands.
780  */
781 struct ice_sw_rule_vsi_list {
782 	struct ice_aqc_sw_rules_elem_hdr hdr;
783 
784 	__le16 index; /* Index of VSI/Prune list */
785 	__le16 number_vsi;
786 	__le16 vsi[]; /* Array of number_vsi VSI numbers */
787 } __packed __aligned(sizeof(__le16));
788 
789 /* Query PFC Mode (direct 0x0302)
790  * Set PFC Mode (direct 0x0303)
791  */
792 struct ice_aqc_set_query_pfc_mode {
793 	u8	pfc_mode;
794 /* For Query Command response, reserved in all other cases */
795 #define ICE_AQC_PFC_VLAN_BASED_PFC	1
796 #define ICE_AQC_PFC_DSCP_BASED_PFC	2
797 	u8	rsvd[15];
798 };
799 /* Get Default Topology (indirect 0x0400) */
800 struct ice_aqc_get_topo {
801 	u8 port_num;
802 	u8 num_branches;
803 	__le16 reserved1;
804 	__le32 reserved2;
805 	__le32 addr_high;
806 	__le32 addr_low;
807 };
808 
809 /* Update TSE (indirect 0x0403)
810  * Get TSE (indirect 0x0404)
811  * Add TSE (indirect 0x0401)
812  * Delete TSE (indirect 0x040F)
813  * Move TSE (indirect 0x0408)
814  * Suspend Nodes (indirect 0x0409)
815  * Resume Nodes (indirect 0x040A)
816  */
817 struct ice_aqc_sched_elem_cmd {
818 	__le16 num_elem_req;	/* Used by commands */
819 	__le16 num_elem_resp;	/* Used by responses */
820 	__le32 reserved;
821 	__le32 addr_high;
822 	__le32 addr_low;
823 };
824 
825 struct ice_aqc_txsched_move_grp_info_hdr {
826 	__le32 src_parent_teid;
827 	__le32 dest_parent_teid;
828 	__le16 num_elems;
829 	u8 mode;
830 #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF		0x0
831 #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN		0x1
832 #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN		0x2
833 	u8 reserved;
834 };
835 
836 struct ice_aqc_move_elem {
837 	struct ice_aqc_txsched_move_grp_info_hdr hdr;
838 	__le32 teid[];
839 };
840 
841 struct ice_aqc_elem_info_bw {
842 	__le16 bw_profile_idx;
843 	__le16 bw_alloc;
844 };
845 
846 struct ice_aqc_txsched_elem {
847 	u8 elem_type; /* Special field, reserved for some aq calls */
848 #define ICE_AQC_ELEM_TYPE_UNDEFINED		0x0
849 #define ICE_AQC_ELEM_TYPE_ROOT_PORT		0x1
850 #define ICE_AQC_ELEM_TYPE_TC			0x2
851 #define ICE_AQC_ELEM_TYPE_SE_GENERIC		0x3
852 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT		0x4
853 #define ICE_AQC_ELEM_TYPE_LEAF			0x5
854 #define ICE_AQC_ELEM_TYPE_SE_PADDED		0x6
855 	u8 valid_sections;
856 #define ICE_AQC_ELEM_VALID_GENERIC		BIT(0)
857 #define ICE_AQC_ELEM_VALID_CIR			BIT(1)
858 #define ICE_AQC_ELEM_VALID_EIR			BIT(2)
859 #define ICE_AQC_ELEM_VALID_SHARED		BIT(3)
860 	u8 generic;
861 #define ICE_AQC_ELEM_GENERIC_MODE_M		0x1
862 #define ICE_AQC_ELEM_GENERIC_PRIO_S		0x1
863 #define ICE_AQC_ELEM_GENERIC_PRIO_M	        GENMASK(3, 1)
864 #define ICE_AQC_ELEM_GENERIC_SP_S		0x4
865 #define ICE_AQC_ELEM_GENERIC_SP_M	        GENMASK(4, 4)
866 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S	0x5
867 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M	\
868 	(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
869 	u8 flags; /* Special field, reserved for some aq calls */
870 #define ICE_AQC_ELEM_FLAG_SUSPEND_M		0x1
871 	struct ice_aqc_elem_info_bw cir_bw;
872 	struct ice_aqc_elem_info_bw eir_bw;
873 	__le16 srl_id;
874 	__le16 reserved2;
875 };
876 
877 struct ice_aqc_txsched_elem_data {
878 	__le32 parent_teid;
879 	__le32 node_teid;
880 	struct ice_aqc_txsched_elem data;
881 };
882 
883 struct ice_aqc_txsched_topo_grp_info_hdr {
884 	__le32 parent_teid;
885 	__le16 num_elems;
886 	__le16 reserved2;
887 };
888 
889 struct ice_aqc_add_elem {
890 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
891 	struct ice_aqc_txsched_elem_data generic[];
892 };
893 
894 struct ice_aqc_get_topo_elem {
895 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
896 	struct ice_aqc_txsched_elem_data
897 		generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
898 };
899 
900 struct ice_aqc_delete_elem {
901 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
902 	__le32 teid[];
903 };
904 
905 /* Query Port ETS (indirect 0x040E)
906  *
907  * This indirect command is used to query port TC node configuration.
908  */
909 struct ice_aqc_query_port_ets {
910 	__le32 port_teid;
911 	__le32 reserved;
912 	__le32 addr_high;
913 	__le32 addr_low;
914 };
915 
916 struct ice_aqc_port_ets_elem {
917 	u8 tc_valid_bits;
918 	u8 reserved[3];
919 	/* 3 bits for UP per TC 0-7, 4th byte reserved */
920 	__le32 up2tc;
921 	u8 tc_bw_share[8];
922 	__le32 port_eir_prof_id;
923 	__le32 port_cir_prof_id;
924 	/* 3 bits per Node priority to TC 0-7, 4th byte reserved */
925 	__le32 tc_node_prio;
926 #define ICE_TC_NODE_PRIO_S	0x4
927 	u8 reserved1[4];
928 	__le32 tc_node_teid[8]; /* Used for response, reserved in command */
929 };
930 
931 /* Rate limiting profile for
932  * Add RL profile (indirect 0x0410)
933  * Query RL profile (indirect 0x0411)
934  * Remove RL profile (indirect 0x0415)
935  * These indirect commands acts on single or multiple
936  * RL profiles with specified data.
937  */
938 struct ice_aqc_rl_profile {
939 	__le16 num_profiles;
940 	__le16 num_processed; /* Only for response. Reserved in Command. */
941 	u8 reserved[4];
942 	__le32 addr_high;
943 	__le32 addr_low;
944 };
945 
946 struct ice_aqc_rl_profile_elem {
947 	u8 level;
948 	u8 flags;
949 #define ICE_AQC_RL_PROFILE_TYPE_S	0x0
950 #define ICE_AQC_RL_PROFILE_TYPE_M	(0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
951 #define ICE_AQC_RL_PROFILE_TYPE_CIR	0
952 #define ICE_AQC_RL_PROFILE_TYPE_EIR	1
953 #define ICE_AQC_RL_PROFILE_TYPE_SRL	2
954 /* The following flag is used for Query RL Profile Data */
955 #define ICE_AQC_RL_PROFILE_INVAL_S	0x7
956 #define ICE_AQC_RL_PROFILE_INVAL_M	(0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
957 
958 	__le16 profile_id;
959 	__le16 max_burst_size;
960 	__le16 rl_multiply;
961 	__le16 wake_up_calc;
962 	__le16 rl_encode;
963 };
964 
965 /* Query Scheduler Resource Allocation (indirect 0x0412)
966  * This indirect command retrieves the scheduler resources allocated by
967  * EMP Firmware to the given PF.
968  */
969 struct ice_aqc_query_txsched_res {
970 	u8 reserved[8];
971 	__le32 addr_high;
972 	__le32 addr_low;
973 };
974 
975 struct ice_aqc_generic_sched_props {
976 	__le16 phys_levels;
977 	__le16 logical_levels;
978 	u8 flattening_bitmap;
979 	u8 max_device_cgds;
980 	u8 max_pf_cgds;
981 	u8 rsvd0;
982 	__le16 rdma_qsets;
983 	u8 rsvd1[22];
984 };
985 
986 struct ice_aqc_layer_props {
987 	u8 logical_layer;
988 	u8 chunk_size;
989 	__le16 max_device_nodes;
990 	__le16 max_pf_nodes;
991 	u8 rsvd0[4];
992 	__le16 max_sibl_grp_sz;
993 	__le16 max_cir_rl_profiles;
994 	__le16 max_eir_rl_profiles;
995 	__le16 max_srl_profiles;
996 	u8 rsvd1[14];
997 };
998 
999 struct ice_aqc_query_txsched_res_resp {
1000 	struct ice_aqc_generic_sched_props sched_props;
1001 	struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1002 };
1003 
1004 /* Get PHY capabilities (indirect 0x0600) */
1005 struct ice_aqc_get_phy_caps {
1006 	u8 lport_num;
1007 	u8 reserved;
1008 	__le16 param0;
1009 	/* 18.0 - Report qualified modules */
1010 #define ICE_AQC_GET_PHY_RQM		BIT(0)
1011 	/* 18.1 - 18.3 : Report mode
1012 	 * 000b - Report NVM capabilities
1013 	 * 001b - Report topology capabilities
1014 	 * 010b - Report SW configured
1015 	 * 100b - Report default capabilities
1016 	 */
1017 #define ICE_AQC_REPORT_MODE_S			1
1018 #define ICE_AQC_REPORT_MODE_M			(7 << ICE_AQC_REPORT_MODE_S)
1019 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA	0
1020 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA		BIT(1)
1021 #define ICE_AQC_REPORT_ACTIVE_CFG		BIT(2)
1022 #define ICE_AQC_REPORT_DFLT_CFG		BIT(3)
1023 	__le32 reserved1;
1024 	__le32 addr_high;
1025 	__le32 addr_low;
1026 };
1027 
1028 /* This is #define of PHY type (Extended):
1029  * The first set of defines is for phy_type_low.
1030  */
1031 #define ICE_PHY_TYPE_LOW_100BASE_TX		BIT_ULL(0)
1032 #define ICE_PHY_TYPE_LOW_100M_SGMII		BIT_ULL(1)
1033 #define ICE_PHY_TYPE_LOW_1000BASE_T		BIT_ULL(2)
1034 #define ICE_PHY_TYPE_LOW_1000BASE_SX		BIT_ULL(3)
1035 #define ICE_PHY_TYPE_LOW_1000BASE_LX		BIT_ULL(4)
1036 #define ICE_PHY_TYPE_LOW_1000BASE_KX		BIT_ULL(5)
1037 #define ICE_PHY_TYPE_LOW_1G_SGMII		BIT_ULL(6)
1038 #define ICE_PHY_TYPE_LOW_2500BASE_T		BIT_ULL(7)
1039 #define ICE_PHY_TYPE_LOW_2500BASE_X		BIT_ULL(8)
1040 #define ICE_PHY_TYPE_LOW_2500BASE_KX		BIT_ULL(9)
1041 #define ICE_PHY_TYPE_LOW_5GBASE_T		BIT_ULL(10)
1042 #define ICE_PHY_TYPE_LOW_5GBASE_KR		BIT_ULL(11)
1043 #define ICE_PHY_TYPE_LOW_10GBASE_T		BIT_ULL(12)
1044 #define ICE_PHY_TYPE_LOW_10G_SFI_DA		BIT_ULL(13)
1045 #define ICE_PHY_TYPE_LOW_10GBASE_SR		BIT_ULL(14)
1046 #define ICE_PHY_TYPE_LOW_10GBASE_LR		BIT_ULL(15)
1047 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1		BIT_ULL(16)
1048 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC	BIT_ULL(17)
1049 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C		BIT_ULL(18)
1050 #define ICE_PHY_TYPE_LOW_25GBASE_T		BIT_ULL(19)
1051 #define ICE_PHY_TYPE_LOW_25GBASE_CR		BIT_ULL(20)
1052 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S		BIT_ULL(21)
1053 #define ICE_PHY_TYPE_LOW_25GBASE_CR1		BIT_ULL(22)
1054 #define ICE_PHY_TYPE_LOW_25GBASE_SR		BIT_ULL(23)
1055 #define ICE_PHY_TYPE_LOW_25GBASE_LR		BIT_ULL(24)
1056 #define ICE_PHY_TYPE_LOW_25GBASE_KR		BIT_ULL(25)
1057 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S		BIT_ULL(26)
1058 #define ICE_PHY_TYPE_LOW_25GBASE_KR1		BIT_ULL(27)
1059 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC	BIT_ULL(28)
1060 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C		BIT_ULL(29)
1061 #define ICE_PHY_TYPE_LOW_40GBASE_CR4		BIT_ULL(30)
1062 #define ICE_PHY_TYPE_LOW_40GBASE_SR4		BIT_ULL(31)
1063 #define ICE_PHY_TYPE_LOW_40GBASE_LR4		BIT_ULL(32)
1064 #define ICE_PHY_TYPE_LOW_40GBASE_KR4		BIT_ULL(33)
1065 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC	BIT_ULL(34)
1066 #define ICE_PHY_TYPE_LOW_40G_XLAUI		BIT_ULL(35)
1067 #define ICE_PHY_TYPE_LOW_50GBASE_CR2		BIT_ULL(36)
1068 #define ICE_PHY_TYPE_LOW_50GBASE_SR2		BIT_ULL(37)
1069 #define ICE_PHY_TYPE_LOW_50GBASE_LR2		BIT_ULL(38)
1070 #define ICE_PHY_TYPE_LOW_50GBASE_KR2		BIT_ULL(39)
1071 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC	BIT_ULL(40)
1072 #define ICE_PHY_TYPE_LOW_50G_LAUI2		BIT_ULL(41)
1073 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC	BIT_ULL(42)
1074 #define ICE_PHY_TYPE_LOW_50G_AUI2		BIT_ULL(43)
1075 #define ICE_PHY_TYPE_LOW_50GBASE_CP		BIT_ULL(44)
1076 #define ICE_PHY_TYPE_LOW_50GBASE_SR		BIT_ULL(45)
1077 #define ICE_PHY_TYPE_LOW_50GBASE_FR		BIT_ULL(46)
1078 #define ICE_PHY_TYPE_LOW_50GBASE_LR		BIT_ULL(47)
1079 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4	BIT_ULL(48)
1080 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC	BIT_ULL(49)
1081 #define ICE_PHY_TYPE_LOW_50G_AUI1		BIT_ULL(50)
1082 #define ICE_PHY_TYPE_LOW_100GBASE_CR4		BIT_ULL(51)
1083 #define ICE_PHY_TYPE_LOW_100GBASE_SR4		BIT_ULL(52)
1084 #define ICE_PHY_TYPE_LOW_100GBASE_LR4		BIT_ULL(53)
1085 #define ICE_PHY_TYPE_LOW_100GBASE_KR4		BIT_ULL(54)
1086 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC	BIT_ULL(55)
1087 #define ICE_PHY_TYPE_LOW_100G_CAUI4		BIT_ULL(56)
1088 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC	BIT_ULL(57)
1089 #define ICE_PHY_TYPE_LOW_100G_AUI4		BIT_ULL(58)
1090 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4	BIT_ULL(59)
1091 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4	BIT_ULL(60)
1092 #define ICE_PHY_TYPE_LOW_100GBASE_CP2		BIT_ULL(61)
1093 #define ICE_PHY_TYPE_LOW_100GBASE_SR2		BIT_ULL(62)
1094 #define ICE_PHY_TYPE_LOW_100GBASE_DR		BIT_ULL(63)
1095 #define ICE_PHY_TYPE_LOW_MAX_INDEX		63
1096 /* The second set of defines is for phy_type_high. */
1097 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4	BIT_ULL(0)
1098 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC	BIT_ULL(1)
1099 #define ICE_PHY_TYPE_HIGH_100G_CAUI2		BIT_ULL(2)
1100 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC	BIT_ULL(3)
1101 #define ICE_PHY_TYPE_HIGH_100G_AUI2		BIT_ULL(4)
1102 #define ICE_PHY_TYPE_HIGH_MAX_INDEX		4
1103 
1104 struct ice_aqc_get_phy_caps_data {
1105 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1106 	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1107 	u8 caps;
1108 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE			BIT(0)
1109 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE			BIT(1)
1110 #define ICE_AQC_PHY_LOW_POWER_MODE			BIT(2)
1111 #define ICE_AQC_PHY_EN_LINK				BIT(3)
1112 #define ICE_AQC_PHY_AN_MODE				BIT(4)
1113 #define ICE_AQC_GET_PHY_EN_MOD_QUAL			BIT(5)
1114 #define ICE_AQC_PHY_EN_AUTO_FEC				BIT(7)
1115 #define ICE_AQC_PHY_CAPS_MASK				ICE_M(0xff, 0)
1116 	u8 low_power_ctrl_an;
1117 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG		BIT(0)
1118 #define ICE_AQC_PHY_AN_EN_CLAUSE28			BIT(1)
1119 #define ICE_AQC_PHY_AN_EN_CLAUSE73			BIT(2)
1120 #define ICE_AQC_PHY_AN_EN_CLAUSE37			BIT(3)
1121 	__le16 eee_cap;
1122 #define ICE_AQC_PHY_EEE_EN_100BASE_TX			BIT(0)
1123 #define ICE_AQC_PHY_EEE_EN_1000BASE_T			BIT(1)
1124 #define ICE_AQC_PHY_EEE_EN_10GBASE_T			BIT(2)
1125 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX			BIT(3)
1126 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR			BIT(4)
1127 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR			BIT(5)
1128 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4			BIT(6)
1129 	__le16 eeer_value;
1130 	u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1131 	u8 phy_fw_ver[8];
1132 	u8 link_fec_options;
1133 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN		BIT(0)
1134 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ		BIT(1)
1135 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ			BIT(2)
1136 #define ICE_AQC_PHY_FEC_25G_KR_REQ			BIT(3)
1137 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ			BIT(4)
1138 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN		BIT(6)
1139 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN		BIT(7)
1140 #define ICE_AQC_PHY_FEC_MASK				ICE_M(0xdf, 0)
1141 	u8 module_compliance_enforcement;
1142 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE			BIT(0)
1143 	u8 extended_compliance_code;
1144 #define ICE_MODULE_TYPE_TOTAL_BYTE			3
1145 	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1146 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS			0xA0
1147 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS		0x80
1148 #define ICE_AQC_MOD_TYPE_IDENT				1
1149 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE	BIT(0)
1150 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE	BIT(1)
1151 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR		BIT(4)
1152 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR		BIT(5)
1153 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM		BIT(6)
1154 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER		BIT(7)
1155 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS			0xA0
1156 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS		0x86
1157 	u8 qualified_module_count;
1158 	u8 rsvd2[7];	/* Bytes 47:41 reserved */
1159 #define ICE_AQC_QUAL_MOD_COUNT_MAX			16
1160 	struct {
1161 		u8 v_oui[3];
1162 		u8 rsvd3;
1163 		u8 v_part[16];
1164 		__le32 v_rev;
1165 		__le64 rsvd4;
1166 	} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1167 };
1168 
1169 /* Set PHY capabilities (direct 0x0601)
1170  * NOTE: This command must be followed by setup link and restart auto-neg
1171  */
1172 struct ice_aqc_set_phy_cfg {
1173 	u8 lport_num;
1174 	u8 reserved[7];
1175 	__le32 addr_high;
1176 	__le32 addr_low;
1177 };
1178 
1179 /* Set PHY config command data structure */
1180 struct ice_aqc_set_phy_cfg_data {
1181 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1182 	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1183 	u8 caps;
1184 #define ICE_AQ_PHY_ENA_VALID_MASK	ICE_M(0xef, 0)
1185 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY	BIT(0)
1186 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY	BIT(1)
1187 #define ICE_AQ_PHY_ENA_LOW_POWER	BIT(2)
1188 #define ICE_AQ_PHY_ENA_LINK		BIT(3)
1189 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT	BIT(5)
1190 #define ICE_AQ_PHY_ENA_LESM		BIT(6)
1191 #define ICE_AQ_PHY_ENA_AUTO_FEC		BIT(7)
1192 	u8 low_power_ctrl_an;
1193 	__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1194 	__le16 eeer_value;
1195 	u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1196 	u8 module_compliance_enforcement;
1197 };
1198 
1199 /* Set MAC Config command data structure (direct 0x0603) */
1200 struct ice_aqc_set_mac_cfg {
1201 	__le16 max_frame_size;
1202 	u8 params;
1203 #define ICE_AQ_SET_MAC_PACE_S		3
1204 #define ICE_AQ_SET_MAC_PACE_M		(0xF << ICE_AQ_SET_MAC_PACE_S)
1205 #define ICE_AQ_SET_MAC_PACE_TYPE_M	BIT(7)
1206 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE	0
1207 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED	ICE_AQ_SET_MAC_PACE_TYPE_M
1208 	u8 tx_tmr_priority;
1209 	__le16 tx_tmr_value;
1210 	__le16 fc_refresh_threshold;
1211 	u8 drop_opts;
1212 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK		BIT(0)
1213 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE		0
1214 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS	BIT(0)
1215 	u8 reserved[7];
1216 };
1217 
1218 /* Restart AN command data structure (direct 0x0605)
1219  * Also used for response, with only the lport_num field present.
1220  */
1221 struct ice_aqc_restart_an {
1222 	u8 lport_num;
1223 	u8 reserved;
1224 	u8 cmd_flags;
1225 #define ICE_AQC_RESTART_AN_LINK_RESTART	BIT(1)
1226 #define ICE_AQC_RESTART_AN_LINK_ENABLE	BIT(2)
1227 	u8 reserved2[13];
1228 };
1229 
1230 /* Get link status (indirect 0x0607), also used for Link Status Event */
1231 struct ice_aqc_get_link_status {
1232 	u8 lport_num;
1233 	u8 reserved;
1234 	__le16 cmd_flags;
1235 #define ICE_AQ_LSE_M			0x3
1236 #define ICE_AQ_LSE_NOP			0x0
1237 #define ICE_AQ_LSE_DIS			0x2
1238 #define ICE_AQ_LSE_ENA			0x3
1239 	/* only response uses this flag */
1240 #define ICE_AQ_LSE_IS_ENABLED		0x1
1241 	__le32 reserved2;
1242 	__le32 addr_high;
1243 	__le32 addr_low;
1244 };
1245 
1246 /* Get link status response data structure, also used for Link Status Event */
1247 struct ice_aqc_get_link_status_data {
1248 	u8 topo_media_conflict;
1249 #define ICE_AQ_LINK_TOPO_CONFLICT	BIT(0)
1250 #define ICE_AQ_LINK_MEDIA_CONFLICT	BIT(1)
1251 #define ICE_AQ_LINK_TOPO_CORRUPT	BIT(2)
1252 #define ICE_AQ_LINK_TOPO_UNREACH_PRT	BIT(4)
1253 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT	BIT(5)
1254 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA	BIT(6)
1255 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA	BIT(7)
1256 	u8 link_cfg_err;
1257 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED	BIT(5)
1258 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE	BIT(6)
1259 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT	BIT(7)
1260 	u8 link_info;
1261 #define ICE_AQ_LINK_UP			BIT(0)	/* Link Status */
1262 #define ICE_AQ_LINK_FAULT		BIT(1)
1263 #define ICE_AQ_LINK_FAULT_TX		BIT(2)
1264 #define ICE_AQ_LINK_FAULT_RX		BIT(3)
1265 #define ICE_AQ_LINK_FAULT_REMOTE	BIT(4)
1266 #define ICE_AQ_LINK_UP_PORT		BIT(5)	/* External Port Link Status */
1267 #define ICE_AQ_MEDIA_AVAILABLE		BIT(6)
1268 #define ICE_AQ_SIGNAL_DETECT		BIT(7)
1269 	u8 an_info;
1270 #define ICE_AQ_AN_COMPLETED		BIT(0)
1271 #define ICE_AQ_LP_AN_ABILITY		BIT(1)
1272 #define ICE_AQ_PD_FAULT			BIT(2)	/* Parallel Detection Fault */
1273 #define ICE_AQ_FEC_EN			BIT(3)
1274 #define ICE_AQ_PHY_LOW_POWER		BIT(4)	/* Low Power State */
1275 #define ICE_AQ_LINK_PAUSE_TX		BIT(5)
1276 #define ICE_AQ_LINK_PAUSE_RX		BIT(6)
1277 #define ICE_AQ_QUALIFIED_MODULE		BIT(7)
1278 	u8 ext_info;
1279 #define ICE_AQ_LINK_PHY_TEMP_ALARM	BIT(0)
1280 #define ICE_AQ_LINK_EXCESSIVE_ERRORS	BIT(1)	/* Excessive Link Errors */
1281 	/* Port Tx Suspended */
1282 #define ICE_AQ_LINK_TX_S		2
1283 #define ICE_AQ_LINK_TX_M		(0x03 << ICE_AQ_LINK_TX_S)
1284 #define ICE_AQ_LINK_TX_ACTIVE		0
1285 #define ICE_AQ_LINK_TX_DRAINED		1
1286 #define ICE_AQ_LINK_TX_FLUSHED		3
1287 	u8 reserved2;
1288 	__le16 max_frame_size;
1289 	u8 cfg;
1290 #define ICE_AQ_LINK_25G_KR_FEC_EN	BIT(0)
1291 #define ICE_AQ_LINK_25G_RS_528_FEC_EN	BIT(1)
1292 #define ICE_AQ_LINK_25G_RS_544_FEC_EN	BIT(2)
1293 #define ICE_AQ_FEC_MASK			ICE_M(0x7, 0)
1294 	/* Pacing Config */
1295 #define ICE_AQ_CFG_PACING_S		3
1296 #define ICE_AQ_CFG_PACING_M		(0xF << ICE_AQ_CFG_PACING_S)
1297 #define ICE_AQ_CFG_PACING_TYPE_M	BIT(7)
1298 #define ICE_AQ_CFG_PACING_TYPE_AVG	0
1299 #define ICE_AQ_CFG_PACING_TYPE_FIXED	ICE_AQ_CFG_PACING_TYPE_M
1300 	/* External Device Power Ability */
1301 	u8 power_desc;
1302 #define ICE_AQ_PWR_CLASS_M		0x3F
1303 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH	0
1304 #define ICE_AQ_LINK_PWR_BASET_HIGH	1
1305 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1	0
1306 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2	1
1307 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3	2
1308 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4	3
1309 	__le16 link_speed;
1310 #define ICE_AQ_LINK_SPEED_M		0x7FF
1311 #define ICE_AQ_LINK_SPEED_10MB		BIT(0)
1312 #define ICE_AQ_LINK_SPEED_100MB		BIT(1)
1313 #define ICE_AQ_LINK_SPEED_1000MB	BIT(2)
1314 #define ICE_AQ_LINK_SPEED_2500MB	BIT(3)
1315 #define ICE_AQ_LINK_SPEED_5GB		BIT(4)
1316 #define ICE_AQ_LINK_SPEED_10GB		BIT(5)
1317 #define ICE_AQ_LINK_SPEED_20GB		BIT(6)
1318 #define ICE_AQ_LINK_SPEED_25GB		BIT(7)
1319 #define ICE_AQ_LINK_SPEED_40GB		BIT(8)
1320 #define ICE_AQ_LINK_SPEED_50GB		BIT(9)
1321 #define ICE_AQ_LINK_SPEED_100GB		BIT(10)
1322 #define ICE_AQ_LINK_SPEED_UNKNOWN	BIT(15)
1323 	__le32 reserved3; /* Aligns next field to 8-byte boundary */
1324 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1325 	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1326 };
1327 
1328 /* Set event mask command (direct 0x0613) */
1329 struct ice_aqc_set_event_mask {
1330 	u8	lport_num;
1331 	u8	reserved[7];
1332 	__le16	event_mask;
1333 #define ICE_AQ_LINK_EVENT_UPDOWN		BIT(1)
1334 #define ICE_AQ_LINK_EVENT_MEDIA_NA		BIT(2)
1335 #define ICE_AQ_LINK_EVENT_LINK_FAULT		BIT(3)
1336 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM	BIT(4)
1337 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS	BIT(5)
1338 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT		BIT(6)
1339 #define ICE_AQ_LINK_EVENT_AN_COMPLETED		BIT(7)
1340 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL	BIT(8)
1341 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED	BIT(9)
1342 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL	BIT(12)
1343 	u8	reserved1[6];
1344 };
1345 
1346 /* Set MAC Loopback command (direct 0x0620) */
1347 struct ice_aqc_set_mac_lb {
1348 	u8 lb_mode;
1349 #define ICE_AQ_MAC_LB_EN		BIT(0)
1350 #define ICE_AQ_MAC_LB_OSC_CLK		BIT(1)
1351 	u8 reserved[15];
1352 };
1353 
1354 struct ice_aqc_link_topo_params {
1355 	u8 lport_num;
1356 	u8 lport_num_valid;
1357 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID	BIT(0)
1358 	u8 node_type_ctx;
1359 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S		0
1360 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M	(0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1361 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY		0
1362 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL	1
1363 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL	2
1364 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL	3
1365 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED		4
1366 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL	5
1367 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE	6
1368 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ	7
1369 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM	8
1370 #define ICE_AQC_LINK_TOPO_NODE_CTX_S		4
1371 #define ICE_AQC_LINK_TOPO_NODE_CTX_M		\
1372 				(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1373 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL	0
1374 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD	1
1375 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT		2
1376 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE		3
1377 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED	4
1378 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE	5
1379 	u8 index;
1380 };
1381 
1382 struct ice_aqc_link_topo_addr {
1383 	struct ice_aqc_link_topo_params topo_params;
1384 	__le16 handle;
1385 #define ICE_AQC_LINK_TOPO_HANDLE_S	0
1386 #define ICE_AQC_LINK_TOPO_HANDLE_M	(0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1387 /* Used to decode the handle field */
1388 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M	BIT(9)
1389 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM	BIT(9)
1390 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ	0
1391 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S		0
1392 /* In case of a Mezzanine type */
1393 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M	\
1394 				(0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1395 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S	6
1396 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M	(0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1397 /* In case of a LOM type */
1398 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M	\
1399 				(0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1400 };
1401 
1402 /* Get Link Topology Handle (direct, 0x06E0) */
1403 struct ice_aqc_get_link_topo {
1404 	struct ice_aqc_link_topo_addr addr;
1405 	u8 node_part_num;
1406 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575	0x21
1407 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827	0x31
1408 	u8 rsvd[9];
1409 };
1410 
1411 /* Read/Write I2C (direct, 0x06E2/0x06E3) */
1412 struct ice_aqc_i2c {
1413 	struct ice_aqc_link_topo_addr topo_addr;
1414 	__le16 i2c_addr;
1415 	u8 i2c_params;
1416 #define ICE_AQC_I2C_DATA_SIZE_M		GENMASK(3, 0)
1417 #define ICE_AQC_I2C_USE_REPEATED_START	BIT(7)
1418 
1419 	u8 rsvd;
1420 	__le16 i2c_bus_addr;
1421 	u8 i2c_data[4]; /* Used only by write command, reserved in read. */
1422 };
1423 
1424 /* Read I2C Response (direct, 0x06E2) */
1425 struct ice_aqc_read_i2c_resp {
1426 	u8 i2c_data[16];
1427 };
1428 
1429 /* Set Port Identification LED (direct, 0x06E9) */
1430 struct ice_aqc_set_port_id_led {
1431 	u8 lport_num;
1432 	u8 lport_num_valid;
1433 	u8 ident_mode;
1434 #define ICE_AQC_PORT_IDENT_LED_BLINK	BIT(0)
1435 #define ICE_AQC_PORT_IDENT_LED_ORIG	0
1436 	u8 rsvd[13];
1437 };
1438 
1439 /* Get Port Options (indirect, 0x06EA) */
1440 struct ice_aqc_get_port_options {
1441 	u8 lport_num;
1442 	u8 lport_num_valid;
1443 	u8 port_options_count;
1444 #define ICE_AQC_PORT_OPT_COUNT_M	GENMASK(3, 0)
1445 #define ICE_AQC_PORT_OPT_MAX		16
1446 
1447 	u8 innermost_phy_index;
1448 	u8 port_options;
1449 #define ICE_AQC_PORT_OPT_ACTIVE_M	GENMASK(3, 0)
1450 #define ICE_AQC_PORT_OPT_VALID		BIT(7)
1451 
1452 	u8 pending_port_option_status;
1453 #define ICE_AQC_PENDING_PORT_OPT_IDX_M	GENMASK(3, 0)
1454 #define ICE_AQC_PENDING_PORT_OPT_VALID	BIT(7)
1455 
1456 	u8 rsvd[2];
1457 	__le32 addr_high;
1458 	__le32 addr_low;
1459 };
1460 
1461 struct ice_aqc_get_port_options_elem {
1462 	u8 pmd;
1463 #define ICE_AQC_PORT_OPT_PMD_COUNT_M	GENMASK(3, 0)
1464 
1465 	u8 max_lane_speed;
1466 #define ICE_AQC_PORT_OPT_MAX_LANE_M	GENMASK(3, 0)
1467 #define ICE_AQC_PORT_OPT_MAX_LANE_100M	0
1468 #define ICE_AQC_PORT_OPT_MAX_LANE_1G	1
1469 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M	2
1470 #define ICE_AQC_PORT_OPT_MAX_LANE_5G	3
1471 #define ICE_AQC_PORT_OPT_MAX_LANE_10G	4
1472 #define ICE_AQC_PORT_OPT_MAX_LANE_25G	5
1473 #define ICE_AQC_PORT_OPT_MAX_LANE_50G	6
1474 #define ICE_AQC_PORT_OPT_MAX_LANE_100G	7
1475 
1476 	u8 global_scid[2];
1477 	u8 phy_scid[2];
1478 	u8 pf2port_cid[2];
1479 };
1480 
1481 /* Set Port Option (direct, 0x06EB) */
1482 struct ice_aqc_set_port_option {
1483 	u8 lport_num;
1484 	u8 lport_num_valid;
1485 	u8 selected_port_option;
1486 	u8 rsvd[13];
1487 };
1488 
1489 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */
1490 struct ice_aqc_gpio {
1491 	__le16 gpio_ctrl_handle;
1492 #define ICE_AQC_GPIO_HANDLE_S	0
1493 #define ICE_AQC_GPIO_HANDLE_M	(0x3FF << ICE_AQC_GPIO_HANDLE_S)
1494 	u8 gpio_num;
1495 	u8 gpio_val;
1496 	u8 rsvd[12];
1497 };
1498 
1499 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1500 struct ice_aqc_sff_eeprom {
1501 	u8 lport_num;
1502 	u8 lport_num_valid;
1503 #define ICE_AQC_SFF_PORT_NUM_VALID	BIT(0)
1504 	__le16 i2c_bus_addr;
1505 #define ICE_AQC_SFF_I2CBUS_7BIT_M	0x7F
1506 #define ICE_AQC_SFF_I2CBUS_10BIT_M	0x3FF
1507 #define ICE_AQC_SFF_I2CBUS_TYPE_M	BIT(10)
1508 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT	0
1509 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT	ICE_AQC_SFF_I2CBUS_TYPE_M
1510 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S	11
1511 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M	(0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1512 #define ICE_AQC_SFF_NO_PAGE_CHANGE	0
1513 #define ICE_AQC_SFF_SET_23_ON_MISMATCH	1
1514 #define ICE_AQC_SFF_SET_22_ON_MISMATCH	2
1515 #define ICE_AQC_SFF_IS_WRITE		BIT(15)
1516 	__le16 i2c_mem_addr;
1517 	__le16 eeprom_page;
1518 #define  ICE_AQC_SFF_EEPROM_BANK_S 0
1519 #define  ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1520 #define  ICE_AQC_SFF_EEPROM_PAGE_S 8
1521 #define  ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1522 	__le32 addr_high;
1523 	__le32 addr_low;
1524 };
1525 
1526 /* NVM Read command (indirect 0x0701)
1527  * NVM Erase commands (direct 0x0702)
1528  * NVM Update commands (indirect 0x0703)
1529  */
1530 struct ice_aqc_nvm {
1531 #define ICE_AQC_NVM_MAX_OFFSET		0xFFFFFF
1532 	__le16 offset_low;
1533 	u8 offset_high;
1534 	u8 cmd_flags;
1535 #define ICE_AQC_NVM_LAST_CMD		BIT(0)
1536 #define ICE_AQC_NVM_PCIR_REQ		BIT(0)	/* Used by NVM Update reply */
1537 #define ICE_AQC_NVM_PRESERVATION_S	1
1538 #define ICE_AQC_NVM_PRESERVATION_M	(3 << ICE_AQC_NVM_PRESERVATION_S)
1539 #define ICE_AQC_NVM_NO_PRESERVATION	(0 << ICE_AQC_NVM_PRESERVATION_S)
1540 #define ICE_AQC_NVM_PRESERVE_ALL	BIT(1)
1541 #define ICE_AQC_NVM_FACTORY_DEFAULT	(2 << ICE_AQC_NVM_PRESERVATION_S)
1542 #define ICE_AQC_NVM_PRESERVE_SELECTED	(3 << ICE_AQC_NVM_PRESERVATION_S)
1543 #define ICE_AQC_NVM_ACTIV_SEL_NVM	BIT(3) /* Write Activate/SR Dump only */
1544 #define ICE_AQC_NVM_ACTIV_SEL_OROM	BIT(4)
1545 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST	BIT(5)
1546 #define ICE_AQC_NVM_SPECIAL_UPDATE	BIT(6)
1547 #define ICE_AQC_NVM_REVERT_LAST_ACTIV	BIT(6) /* Write Activate only */
1548 #define ICE_AQC_NVM_ACTIV_SEL_MASK	ICE_M(0x7, 3)
1549 #define ICE_AQC_NVM_FLASH_ONLY		BIT(7)
1550 #define ICE_AQC_NVM_RESET_LVL_M		ICE_M(0x3, 0) /* Write reply only */
1551 #define ICE_AQC_NVM_POR_FLAG		0
1552 #define ICE_AQC_NVM_PERST_FLAG		1
1553 #define ICE_AQC_NVM_EMPR_FLAG		2
1554 #define ICE_AQC_NVM_EMPR_ENA		BIT(0) /* Write Activate reply only */
1555 	/* For Write Activate, several flags are sent as part of a separate
1556 	 * flags2 field using a separate byte. For simplicity of the software
1557 	 * interface, we pass the flags as a 16 bit value so these flags are
1558 	 * all offset by 8 bits
1559 	 */
1560 #define ICE_AQC_NVM_ACTIV_REQ_EMPR	BIT(8) /* NVM Write Activate only */
1561 	__le16 module_typeid;
1562 	__le16 length;
1563 #define ICE_AQC_NVM_ERASE_LEN	0xFFFF
1564 	__le32 addr_high;
1565 	__le32 addr_low;
1566 };
1567 
1568 #define ICE_AQC_NVM_START_POINT			0
1569 
1570 /* NVM Checksum Command (direct, 0x0706) */
1571 struct ice_aqc_nvm_checksum {
1572 	u8 flags;
1573 #define ICE_AQC_NVM_CHECKSUM_VERIFY	BIT(0)
1574 #define ICE_AQC_NVM_CHECKSUM_RECALC	BIT(1)
1575 	u8 rsvd;
1576 	__le16 checksum; /* Used only by response */
1577 #define ICE_AQC_NVM_CHECKSUM_CORRECT	0xBABA
1578 	u8 rsvd2[12];
1579 };
1580 
1581 /* Used for NVM Set Package Data command - 0x070A */
1582 struct ice_aqc_nvm_pkg_data {
1583 	u8 reserved[3];
1584 	u8 cmd_flags;
1585 #define ICE_AQC_NVM_PKG_DELETE		BIT(0) /* used for command call */
1586 #define ICE_AQC_NVM_PKG_SKIPPED		BIT(0) /* used for command response */
1587 
1588 	u32 reserved1;
1589 	__le32 addr_high;
1590 	__le32 addr_low;
1591 };
1592 
1593 /* Used for Pass Component Table command - 0x070B */
1594 struct ice_aqc_nvm_pass_comp_tbl {
1595 	u8 component_response; /* Response only */
1596 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED		0x0
1597 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE	0x1
1598 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED		0x2
1599 	u8 component_response_code; /* Response only */
1600 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE	0x0
1601 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE	0x1
1602 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER		0x2
1603 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE		0x3
1604 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE		0x4
1605 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE	0x5
1606 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE		0x6
1607 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE	0x7
1608 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE	0x8
1609 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE	0xA
1610 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE		0xB
1611 	u8 reserved;
1612 	u8 transfer_flag;
1613 #define ICE_AQ_NVM_PASS_COMP_TBL_START			0x1
1614 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE			0x2
1615 #define ICE_AQ_NVM_PASS_COMP_TBL_END			0x4
1616 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END		0x5
1617 	__le32 reserved1;
1618 	__le32 addr_high;
1619 	__le32 addr_low;
1620 };
1621 
1622 struct ice_aqc_nvm_comp_tbl {
1623 	__le16 comp_class;
1624 #define NVM_COMP_CLASS_ALL_FW	0x000A
1625 
1626 	__le16 comp_id;
1627 #define NVM_COMP_ID_OROM	0x5
1628 #define NVM_COMP_ID_NVM		0x6
1629 #define NVM_COMP_ID_NETLIST	0x8
1630 
1631 	u8 comp_class_idx;
1632 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1633 
1634 	__le32 comp_cmp_stamp;
1635 	u8 cvs_type;
1636 #define NVM_CVS_TYPE_ASCII	0x1
1637 
1638 	u8 cvs_len;
1639 	u8 cvs[]; /* Component Version String */
1640 } __packed;
1641 
1642 /* Send to PF command (indirect 0x0801) ID is only used by PF
1643  *
1644  * Send to VF command (indirect 0x0802) ID is only used by PF
1645  *
1646  */
1647 struct ice_aqc_pf_vf_msg {
1648 	__le32 id;
1649 	u32 reserved;
1650 	__le32 addr_high;
1651 	__le32 addr_low;
1652 };
1653 
1654 /* Get LLDP MIB (indirect 0x0A00)
1655  * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1656  * as the format is the same.
1657  */
1658 struct ice_aqc_lldp_get_mib {
1659 	u8 type;
1660 #define ICE_AQ_LLDP_MIB_TYPE_S			0
1661 #define ICE_AQ_LLDP_MIB_TYPE_M			(0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1662 #define ICE_AQ_LLDP_MIB_LOCAL			0
1663 #define ICE_AQ_LLDP_MIB_REMOTE			1
1664 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE	2
1665 #define ICE_AQ_LLDP_BRID_TYPE_S			2
1666 #define ICE_AQ_LLDP_BRID_TYPE_M			(0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1667 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID	0
1668 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR		1
1669 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1670 #define ICE_AQ_LLDP_TX_S			0x4
1671 #define ICE_AQ_LLDP_TX_M			(0x03 << ICE_AQ_LLDP_TX_S)
1672 #define ICE_AQ_LLDP_TX_ACTIVE			0
1673 #define ICE_AQ_LLDP_TX_SUSPENDED		1
1674 #define ICE_AQ_LLDP_TX_FLUSHED			3
1675 /* DCBX mode */
1676 #define ICE_AQ_LLDP_DCBX_M			GENMASK(7, 6)
1677 #define ICE_AQ_LLDP_DCBX_NA			0
1678 #define ICE_AQ_LLDP_DCBX_CEE			1
1679 #define ICE_AQ_LLDP_DCBX_IEEE			2
1680 
1681 	u8 state;
1682 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M		BIT(0)
1683 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED		0
1684 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING		1
1685 
1686 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1687  * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1688  * Get LLDP MIB (0x0A00) response only.
1689  */
1690 	__le16 local_len;
1691 	__le16 remote_len;
1692 	u8 reserved[2];
1693 	__le32 addr_high;
1694 	__le32 addr_low;
1695 };
1696 
1697 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1698 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1699 struct ice_aqc_lldp_set_mib_change {
1700 	u8 command;
1701 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE		0x0
1702 #define ICE_AQ_LLDP_MIB_UPDATE_DIS		0x1
1703 #define ICE_AQ_LLDP_MIB_PENDING_M		BIT(1)
1704 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE		0
1705 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE		1
1706 	u8 reserved[15];
1707 };
1708 
1709 /* Stop LLDP (direct 0x0A05) */
1710 struct ice_aqc_lldp_stop {
1711 	u8 command;
1712 #define ICE_AQ_LLDP_AGENT_STATE_MASK	BIT(0)
1713 #define ICE_AQ_LLDP_AGENT_STOP		0x0
1714 #define ICE_AQ_LLDP_AGENT_SHUTDOWN	ICE_AQ_LLDP_AGENT_STATE_MASK
1715 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS	BIT(1)
1716 	u8 reserved[15];
1717 };
1718 
1719 /* Start LLDP (direct 0x0A06) */
1720 struct ice_aqc_lldp_start {
1721 	u8 command;
1722 #define ICE_AQ_LLDP_AGENT_START		BIT(0)
1723 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA	BIT(1)
1724 	u8 reserved[15];
1725 };
1726 
1727 /* Get CEE DCBX Oper Config (0x0A07)
1728  * The command uses the generic descriptor struct and
1729  * returns the struct below as an indirect response.
1730  */
1731 struct ice_aqc_get_cee_dcb_cfg_resp {
1732 	u8 oper_num_tc;
1733 	u8 oper_prio_tc[4];
1734 	u8 oper_tc_bw[8];
1735 	u8 oper_pfc_en;
1736 	__le16 oper_app_prio;
1737 #define ICE_AQC_CEE_APP_FCOE_S		0
1738 #define ICE_AQC_CEE_APP_FCOE_M		(0x7 << ICE_AQC_CEE_APP_FCOE_S)
1739 #define ICE_AQC_CEE_APP_ISCSI_S		3
1740 #define ICE_AQC_CEE_APP_ISCSI_M		(0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1741 #define ICE_AQC_CEE_APP_FIP_S		8
1742 #define ICE_AQC_CEE_APP_FIP_M		(0x7 << ICE_AQC_CEE_APP_FIP_S)
1743 	__le32 tlv_status;
1744 #define ICE_AQC_CEE_PG_STATUS_S		0
1745 #define ICE_AQC_CEE_PG_STATUS_M		(0x7 << ICE_AQC_CEE_PG_STATUS_S)
1746 #define ICE_AQC_CEE_PFC_STATUS_S	3
1747 #define ICE_AQC_CEE_PFC_STATUS_M	(0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1748 #define ICE_AQC_CEE_FCOE_STATUS_S	8
1749 #define ICE_AQC_CEE_FCOE_STATUS_M	(0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1750 #define ICE_AQC_CEE_ISCSI_STATUS_S	11
1751 #define ICE_AQC_CEE_ISCSI_STATUS_M	(0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1752 #define ICE_AQC_CEE_FIP_STATUS_S	16
1753 #define ICE_AQC_CEE_FIP_STATUS_M	(0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1754 	u8 reserved[12];
1755 };
1756 
1757 /* Set Local LLDP MIB (indirect 0x0A08)
1758  * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1759  */
1760 struct ice_aqc_lldp_set_local_mib {
1761 	u8 type;
1762 #define SET_LOCAL_MIB_TYPE_DCBX_M		BIT(0)
1763 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB		0
1764 #define SET_LOCAL_MIB_TYPE_CEE_M		BIT(1)
1765 #define SET_LOCAL_MIB_TYPE_CEE_WILLING		0
1766 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING	SET_LOCAL_MIB_TYPE_CEE_M
1767 	u8 reserved0;
1768 	__le16 length;
1769 	u8 reserved1[4];
1770 	__le32 addr_high;
1771 	__le32 addr_low;
1772 };
1773 
1774 /* Stop/Start LLDP Agent (direct 0x0A09)
1775  * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1776  * The same structure is used for the response, with the command field
1777  * being used as the status field.
1778  */
1779 struct ice_aqc_lldp_stop_start_specific_agent {
1780 	u8 command;
1781 #define ICE_AQC_START_STOP_AGENT_M		BIT(0)
1782 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX	0
1783 #define ICE_AQC_START_STOP_AGENT_START_DCBX	ICE_AQC_START_STOP_AGENT_M
1784 	u8 reserved[15];
1785 };
1786 
1787 /* LLDP Filter Control (direct 0x0A0A) */
1788 struct ice_aqc_lldp_filter_ctrl {
1789 	u8 cmd_flags;
1790 #define ICE_AQC_LLDP_FILTER_ACTION_ADD		0x0
1791 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE	0x1
1792 	u8 reserved1;
1793 	__le16 vsi_num;
1794 	u8 reserved2[12];
1795 };
1796 
1797 #define ICE_AQC_RSS_VSI_VALID BIT(15)
1798 
1799 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1800 struct ice_aqc_get_set_rss_key {
1801 	__le16 vsi_id;
1802 	u8 reserved[6];
1803 	__le32 addr_high;
1804 	__le32 addr_low;
1805 };
1806 
1807 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE	0x28
1808 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE	0xC
1809 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1810 				(ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1811 				 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1812 
1813 struct ice_aqc_get_set_rss_keys {
1814 	u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1815 	u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1816 };
1817 
1818 enum ice_lut_type {
1819 	ICE_LUT_VSI = 0,
1820 	ICE_LUT_PF = 1,
1821 	ICE_LUT_GLOBAL = 2,
1822 };
1823 
1824 enum ice_lut_size {
1825 	ICE_LUT_VSI_SIZE = 64,
1826 	ICE_LUT_GLOBAL_SIZE = 512,
1827 	ICE_LUT_PF_SIZE = 2048,
1828 };
1829 
1830 /* enum ice_aqc_lut_flags combines constants used to fill
1831  * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID,
1832  * LUT size and LUT type, last of which does not need neither shift nor mask.
1833  */
1834 enum ice_aqc_lut_flags {
1835 	ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */
1836 	ICE_AQC_LUT_SIZE_512 = BIT(2),
1837 	ICE_AQC_LUT_SIZE_2K = BIT(3),
1838 
1839 	ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4),
1840 };
1841 
1842 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1843 struct ice_aqc_get_set_rss_lut {
1844 	__le16 vsi_id;
1845 	__le16 flags;
1846 	__le32 reserved;
1847 	__le32 addr_high;
1848 	__le32 addr_low;
1849 };
1850 
1851 /* Sideband Control Interface Commands */
1852 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */
1853 struct ice_aqc_neigh_dev_req {
1854 	__le16 sb_data_len;
1855 	u8 reserved[6];
1856 	__le32 addr_high;
1857 	__le32 addr_low;
1858 };
1859 
1860 /* Add Tx LAN Queues (indirect 0x0C30) */
1861 struct ice_aqc_add_txqs {
1862 	u8 num_qgrps;
1863 	u8 reserved[3];
1864 	__le32 reserved1;
1865 	__le32 addr_high;
1866 	__le32 addr_low;
1867 };
1868 
1869 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1870  * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1871  */
1872 struct ice_aqc_add_txqs_perq {
1873 	__le16 txq_id;
1874 	u8 rsvd[2];
1875 	__le32 q_teid;
1876 	u8 txq_ctx[22];
1877 	u8 rsvd2[2];
1878 	struct ice_aqc_txsched_elem info;
1879 };
1880 
1881 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1882  * is an array of the following structs. Please note that the length of
1883  * each struct ice_aqc_add_tx_qgrp is variable due
1884  * to the variable number of queues in each group!
1885  */
1886 struct ice_aqc_add_tx_qgrp {
1887 	__le32 parent_teid;
1888 	u8 num_txqs;
1889 	u8 rsvd[3];
1890 	struct ice_aqc_add_txqs_perq txqs[];
1891 };
1892 
1893 /* Disable Tx LAN Queues (indirect 0x0C31) */
1894 struct ice_aqc_dis_txqs {
1895 	u8 cmd_type;
1896 #define ICE_AQC_Q_DIS_CMD_S		0
1897 #define ICE_AQC_Q_DIS_CMD_M		(0x3 << ICE_AQC_Q_DIS_CMD_S)
1898 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET	(0 << ICE_AQC_Q_DIS_CMD_S)
1899 #define ICE_AQC_Q_DIS_CMD_VM_RESET	BIT(ICE_AQC_Q_DIS_CMD_S)
1900 #define ICE_AQC_Q_DIS_CMD_VF_RESET	(2 << ICE_AQC_Q_DIS_CMD_S)
1901 #define ICE_AQC_Q_DIS_CMD_PF_RESET	(3 << ICE_AQC_Q_DIS_CMD_S)
1902 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL	BIT(2)
1903 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE	BIT(3)
1904 	u8 num_entries;
1905 	__le16 vmvf_and_timeout;
1906 #define ICE_AQC_Q_DIS_VMVF_NUM_S	0
1907 #define ICE_AQC_Q_DIS_VMVF_NUM_M	(0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1908 #define ICE_AQC_Q_DIS_TIMEOUT_S		10
1909 #define ICE_AQC_Q_DIS_TIMEOUT_M		(0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1910 	__le32 blocked_cgds;
1911 	__le32 addr_high;
1912 	__le32 addr_low;
1913 };
1914 
1915 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1916  * contains the following structures, arrayed one after the
1917  * other.
1918  * Note: Since the q_id is 16 bits wide, if the
1919  * number of queues is even, then 2 bytes of alignment MUST be
1920  * added before the start of the next group, to allow correct
1921  * alignment of the parent_teid field.
1922  */
1923 struct ice_aqc_dis_txq_item {
1924 	__le32 parent_teid;
1925 	u8 num_qs;
1926 	u8 rsvd;
1927 	/* The length of the q_id array varies according to num_qs */
1928 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S		15
1929 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q	\
1930 			(0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1931 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET	\
1932 			(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1933 	__le16 q_id[];
1934 } __packed;
1935 
1936 /* Move/Reconfigure Tx queue (indirect 0x0C32) */
1937 struct ice_aqc_cfg_txqs {
1938 	u8 cmd_type;
1939 #define ICE_AQC_Q_CFG_MOVE_NODE		0x1
1940 #define ICE_AQC_Q_CFG_TC_CHNG		0x2
1941 #define ICE_AQC_Q_CFG_MOVE_TC_CHNG	0x3
1942 #define ICE_AQC_Q_CFG_SUBSEQ_CALL	BIT(2)
1943 #define ICE_AQC_Q_CFG_FLUSH		BIT(3)
1944 	u8 num_qs;
1945 	u8 port_num_chng;
1946 #define ICE_AQC_Q_CFG_SRC_PRT_M		0x7
1947 #define ICE_AQC_Q_CFG_DST_PRT_S		3
1948 #define ICE_AQC_Q_CFG_DST_PRT_M		(0x7 << ICE_AQC_Q_CFG_DST_PRT_S)
1949 	u8 time_out;
1950 #define ICE_AQC_Q_CFG_TIMEOUT_S		2
1951 #define ICE_AQC_Q_CFG_TIMEOUT_M		(0x1F << ICE_AQC_Q_CFG_TIMEOUT_S)
1952 	__le32 blocked_cgds;
1953 	__le32 addr_high;
1954 	__le32 addr_low;
1955 };
1956 
1957 /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */
1958 struct ice_aqc_cfg_txq_perq {
1959 	__le16 q_handle;
1960 	u8 tc;
1961 	u8 rsvd;
1962 	__le32 q_teid;
1963 };
1964 
1965 /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */
1966 struct ice_aqc_cfg_txqs_buf {
1967 	__le32 src_parent_teid;
1968 	__le32 dst_parent_teid;
1969 	struct ice_aqc_cfg_txq_perq queue_info[];
1970 };
1971 
1972 /* Add Tx RDMA Queue Set (indirect 0x0C33) */
1973 struct ice_aqc_add_rdma_qset {
1974 	u8 num_qset_grps;
1975 	u8 reserved[7];
1976 	__le32 addr_high;
1977 	__le32 addr_low;
1978 };
1979 
1980 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set
1981  * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
1982  */
1983 struct ice_aqc_add_tx_rdma_qset_entry {
1984 	__le16 tx_qset_id;
1985 	u8 rsvd[2];
1986 	__le32 qset_teid;
1987 	struct ice_aqc_txsched_elem info;
1988 };
1989 
1990 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
1991  * is an array of the following structs. Please note that the length of
1992  * each struct ice_aqc_add_rdma_qset is variable due to the variable
1993  * number of queues in each group!
1994  */
1995 struct ice_aqc_add_rdma_qset_data {
1996 	__le32 parent_teid;
1997 	__le16 num_qsets;
1998 	u8 rsvd[2];
1999 	struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];
2000 };
2001 
2002 /* Configure Firmware Logging Command (indirect 0xFF09)
2003  * Logging Information Read Response (indirect 0xFF10)
2004  * Note: The 0xFF10 command has no input parameters.
2005  */
2006 struct ice_aqc_fw_logging {
2007 	u8 log_ctrl;
2008 #define ICE_AQC_FW_LOG_AQ_EN		BIT(0)
2009 #define ICE_AQC_FW_LOG_UART_EN		BIT(1)
2010 	u8 rsvd0;
2011 	u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
2012 #define ICE_AQC_FW_LOG_AQ_VALID		BIT(0)
2013 #define ICE_AQC_FW_LOG_UART_VALID	BIT(1)
2014 	u8 rsvd1[5];
2015 	__le32 addr_high;
2016 	__le32 addr_low;
2017 };
2018 
2019 enum ice_aqc_fw_logging_mod {
2020 	ICE_AQC_FW_LOG_ID_GENERAL = 0,
2021 	ICE_AQC_FW_LOG_ID_CTRL,
2022 	ICE_AQC_FW_LOG_ID_LINK,
2023 	ICE_AQC_FW_LOG_ID_LINK_TOPO,
2024 	ICE_AQC_FW_LOG_ID_DNL,
2025 	ICE_AQC_FW_LOG_ID_I2C,
2026 	ICE_AQC_FW_LOG_ID_SDP,
2027 	ICE_AQC_FW_LOG_ID_MDIO,
2028 	ICE_AQC_FW_LOG_ID_ADMINQ,
2029 	ICE_AQC_FW_LOG_ID_HDMA,
2030 	ICE_AQC_FW_LOG_ID_LLDP,
2031 	ICE_AQC_FW_LOG_ID_DCBX,
2032 	ICE_AQC_FW_LOG_ID_DCB,
2033 	ICE_AQC_FW_LOG_ID_NETPROXY,
2034 	ICE_AQC_FW_LOG_ID_NVM,
2035 	ICE_AQC_FW_LOG_ID_AUTH,
2036 	ICE_AQC_FW_LOG_ID_VPD,
2037 	ICE_AQC_FW_LOG_ID_IOSF,
2038 	ICE_AQC_FW_LOG_ID_PARSER,
2039 	ICE_AQC_FW_LOG_ID_SW,
2040 	ICE_AQC_FW_LOG_ID_SCHEDULER,
2041 	ICE_AQC_FW_LOG_ID_TXQ,
2042 	ICE_AQC_FW_LOG_ID_RSVD,
2043 	ICE_AQC_FW_LOG_ID_POST,
2044 	ICE_AQC_FW_LOG_ID_WATCHDOG,
2045 	ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
2046 	ICE_AQC_FW_LOG_ID_MNG,
2047 	ICE_AQC_FW_LOG_ID_MAX,
2048 };
2049 
2050 /* Defines for both above FW logging command/response buffers */
2051 #define ICE_AQC_FW_LOG_ID_S		0
2052 #define ICE_AQC_FW_LOG_ID_M		(0xFFF << ICE_AQC_FW_LOG_ID_S)
2053 
2054 #define ICE_AQC_FW_LOG_CONF_SUCCESS	0	/* Used by response */
2055 #define ICE_AQC_FW_LOG_CONF_BAD_INDX	BIT(12)	/* Used by response */
2056 
2057 #define ICE_AQC_FW_LOG_EN_S		12
2058 #define ICE_AQC_FW_LOG_EN_M		(0xF << ICE_AQC_FW_LOG_EN_S)
2059 #define ICE_AQC_FW_LOG_INFO_EN		BIT(12)	/* Used by command */
2060 #define ICE_AQC_FW_LOG_INIT_EN		BIT(13)	/* Used by command */
2061 #define ICE_AQC_FW_LOG_FLOW_EN		BIT(14)	/* Used by command */
2062 #define ICE_AQC_FW_LOG_ERR_EN		BIT(15)	/* Used by command */
2063 
2064 /* Get/Clear FW Log (indirect 0xFF11) */
2065 struct ice_aqc_get_clear_fw_log {
2066 	u8 flags;
2067 #define ICE_AQC_FW_LOG_CLEAR		BIT(0)
2068 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL	BIT(1)
2069 	u8 rsvd1[7];
2070 	__le32 addr_high;
2071 	__le32 addr_low;
2072 };
2073 
2074 /* Download Package (indirect 0x0C40) */
2075 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */
2076 struct ice_aqc_download_pkg {
2077 	u8 flags;
2078 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF	0x01
2079 	u8 reserved[3];
2080 	__le32 reserved1;
2081 	__le32 addr_high;
2082 	__le32 addr_low;
2083 };
2084 
2085 struct ice_aqc_download_pkg_resp {
2086 	__le32 error_offset;
2087 	__le32 error_info;
2088 	__le32 addr_high;
2089 	__le32 addr_low;
2090 };
2091 
2092 /* Get Package Info List (indirect 0x0C43) */
2093 struct ice_aqc_get_pkg_info_list {
2094 	__le32 reserved1;
2095 	__le32 reserved2;
2096 	__le32 addr_high;
2097 	__le32 addr_low;
2098 };
2099 
2100 /* Version format for packages */
2101 struct ice_pkg_ver {
2102 	u8 major;
2103 	u8 minor;
2104 	u8 update;
2105 	u8 draft;
2106 };
2107 
2108 #define ICE_PKG_NAME_SIZE	32
2109 #define ICE_SEG_ID_SIZE		28
2110 #define ICE_SEG_NAME_SIZE	28
2111 
2112 struct ice_aqc_get_pkg_info {
2113 	struct ice_pkg_ver ver;
2114 	char name[ICE_SEG_NAME_SIZE];
2115 	__le32 track_id;
2116 	u8 is_in_nvm;
2117 	u8 is_active;
2118 	u8 is_active_at_boot;
2119 	u8 is_modified;
2120 };
2121 
2122 /* Get Package Info List response buffer format (0x0C43) */
2123 struct ice_aqc_get_pkg_info_resp {
2124 	__le32 count;
2125 	struct ice_aqc_get_pkg_info pkg_info[];
2126 };
2127 
2128 /* Driver Shared Parameters (direct, 0x0C90) */
2129 struct ice_aqc_driver_shared_params {
2130 	u8 set_or_get_op;
2131 #define ICE_AQC_DRIVER_PARAM_OP_MASK		BIT(0)
2132 #define ICE_AQC_DRIVER_PARAM_SET		0
2133 #define ICE_AQC_DRIVER_PARAM_GET		1
2134 	u8 param_indx;
2135 #define ICE_AQC_DRIVER_PARAM_MAX_IDX		15
2136 	u8 rsvd[2];
2137 	__le32 param_val;
2138 	__le32 addr_high;
2139 	__le32 addr_low;
2140 };
2141 
2142 enum ice_aqc_driver_params {
2143 	/* OS clock index for PTP timer Domain 0 */
2144 	ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0,
2145 	/* OS clock index for PTP timer Domain 1 */
2146 	ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1,
2147 
2148 	/* Add new parameters above */
2149 	ICE_AQC_DRIVER_PARAM_MAX = 16,
2150 };
2151 
2152 /* Lan Queue Overflow Event (direct, 0x1001) */
2153 struct ice_aqc_event_lan_overflow {
2154 	__le32 prtdcb_ruptq;
2155 	__le32 qtx_ctl;
2156 	u8 reserved[8];
2157 };
2158 
2159 /**
2160  * struct ice_aq_desc - Admin Queue (AQ) descriptor
2161  * @flags: ICE_AQ_FLAG_* flags
2162  * @opcode: AQ command opcode
2163  * @datalen: length in bytes of indirect/external data buffer
2164  * @retval: return value from firmware
2165  * @cookie_high: opaque data high-half
2166  * @cookie_low: opaque data low-half
2167  * @params: command-specific parameters
2168  *
2169  * Descriptor format for commands the driver posts on the Admin Transmit Queue
2170  * (ATQ). The firmware writes back onto the command descriptor and returns
2171  * the result of the command. Asynchronous events that are not an immediate
2172  * result of the command are written to the Admin Receive Queue (ARQ) using
2173  * the same descriptor format. Descriptors are in little-endian notation with
2174  * 32-bit words.
2175  */
2176 struct ice_aq_desc {
2177 	__le16 flags;
2178 	__le16 opcode;
2179 	__le16 datalen;
2180 	__le16 retval;
2181 	__le32 cookie_high;
2182 	__le32 cookie_low;
2183 	union {
2184 		u8 raw[16];
2185 		struct ice_aqc_generic generic;
2186 		struct ice_aqc_get_ver get_ver;
2187 		struct ice_aqc_driver_ver driver_ver;
2188 		struct ice_aqc_q_shutdown q_shutdown;
2189 		struct ice_aqc_req_res res_owner;
2190 		struct ice_aqc_manage_mac_read mac_read;
2191 		struct ice_aqc_manage_mac_write mac_write;
2192 		struct ice_aqc_clear_pxe clear_pxe;
2193 		struct ice_aqc_list_caps get_cap;
2194 		struct ice_aqc_get_phy_caps get_phy;
2195 		struct ice_aqc_set_phy_cfg set_phy;
2196 		struct ice_aqc_restart_an restart_an;
2197 		struct ice_aqc_gpio read_write_gpio;
2198 		struct ice_aqc_sff_eeprom read_write_sff_param;
2199 		struct ice_aqc_set_port_id_led set_port_id_led;
2200 		struct ice_aqc_get_port_options get_port_options;
2201 		struct ice_aqc_set_port_option set_port_option;
2202 		struct ice_aqc_get_sw_cfg get_sw_conf;
2203 		struct ice_aqc_set_port_params set_port_params;
2204 		struct ice_aqc_sw_rules sw_rules;
2205 		struct ice_aqc_add_get_recipe add_get_recipe;
2206 		struct ice_aqc_recipe_to_profile recipe_to_profile;
2207 		struct ice_aqc_get_topo get_topo;
2208 		struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2209 		struct ice_aqc_query_txsched_res query_sched_res;
2210 		struct ice_aqc_query_port_ets port_ets;
2211 		struct ice_aqc_rl_profile rl_profile;
2212 		struct ice_aqc_nvm nvm;
2213 		struct ice_aqc_nvm_checksum nvm_checksum;
2214 		struct ice_aqc_nvm_pkg_data pkg_data;
2215 		struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
2216 		struct ice_aqc_pf_vf_msg virt;
2217 		struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2218 		struct ice_aqc_lldp_get_mib lldp_get_mib;
2219 		struct ice_aqc_lldp_set_mib_change lldp_set_event;
2220 		struct ice_aqc_lldp_stop lldp_stop;
2221 		struct ice_aqc_lldp_start lldp_start;
2222 		struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2223 		struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2224 		struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2225 		struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2226 		struct ice_aqc_get_set_rss_key get_set_rss_key;
2227 		struct ice_aqc_neigh_dev_req neigh_dev;
2228 		struct ice_aqc_add_txqs add_txqs;
2229 		struct ice_aqc_dis_txqs dis_txqs;
2230 		struct ice_aqc_cfg_txqs cfg_txqs;
2231 		struct ice_aqc_add_rdma_qset add_rdma_qset;
2232 		struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2233 		struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2234 		struct ice_aqc_fw_logging fw_logging;
2235 		struct ice_aqc_get_clear_fw_log get_clear_fw_log;
2236 		struct ice_aqc_download_pkg download_pkg;
2237 		struct ice_aqc_driver_shared_params drv_shared_params;
2238 		struct ice_aqc_set_mac_lb set_mac_lb;
2239 		struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2240 		struct ice_aqc_set_mac_cfg set_mac_cfg;
2241 		struct ice_aqc_set_event_mask set_event_mask;
2242 		struct ice_aqc_get_link_status get_link_status;
2243 		struct ice_aqc_event_lan_overflow lan_overflow;
2244 		struct ice_aqc_get_link_topo get_link_topo;
2245 		struct ice_aqc_i2c read_write_i2c;
2246 		struct ice_aqc_read_i2c_resp read_i2c_resp;
2247 	} params;
2248 };
2249 
2250 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2251 #define ICE_AQ_LG_BUF	512
2252 
2253 #define ICE_AQ_FLAG_ERR_S	2
2254 #define ICE_AQ_FLAG_LB_S	9
2255 #define ICE_AQ_FLAG_RD_S	10
2256 #define ICE_AQ_FLAG_BUF_S	12
2257 #define ICE_AQ_FLAG_SI_S	13
2258 
2259 #define ICE_AQ_FLAG_ERR		BIT(ICE_AQ_FLAG_ERR_S) /* 0x4    */
2260 #define ICE_AQ_FLAG_LB		BIT(ICE_AQ_FLAG_LB_S)  /* 0x200  */
2261 #define ICE_AQ_FLAG_RD		BIT(ICE_AQ_FLAG_RD_S)  /* 0x400  */
2262 #define ICE_AQ_FLAG_BUF		BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2263 #define ICE_AQ_FLAG_SI		BIT(ICE_AQ_FLAG_SI_S)  /* 0x2000 */
2264 
2265 /* error codes */
2266 enum ice_aq_err {
2267 	ICE_AQ_RC_OK		= 0,  /* Success */
2268 	ICE_AQ_RC_EPERM		= 1,  /* Operation not permitted */
2269 	ICE_AQ_RC_ENOENT	= 2,  /* No such element */
2270 	ICE_AQ_RC_ENOMEM	= 9,  /* Out of memory */
2271 	ICE_AQ_RC_EBUSY		= 12, /* Device or resource busy */
2272 	ICE_AQ_RC_EEXIST	= 13, /* Object already exists */
2273 	ICE_AQ_RC_EINVAL	= 14, /* Invalid argument */
2274 	ICE_AQ_RC_ENOSPC	= 16, /* No space left or allocation failure */
2275 	ICE_AQ_RC_ENOSYS	= 17, /* Function not implemented */
2276 	ICE_AQ_RC_EMODE		= 21, /* Op not allowed in current dev mode */
2277 	ICE_AQ_RC_ENOSEC	= 24, /* Missing security manifest */
2278 	ICE_AQ_RC_EBADSIG	= 25, /* Bad RSA signature */
2279 	ICE_AQ_RC_ESVN		= 26, /* SVN number prohibits this package */
2280 	ICE_AQ_RC_EBADMAN	= 27, /* Manifest hash mismatch */
2281 	ICE_AQ_RC_EBADBUF	= 28, /* Buffer hash mismatches manifest */
2282 };
2283 
2284 /* Admin Queue command opcodes */
2285 enum ice_adminq_opc {
2286 	/* AQ commands */
2287 	ice_aqc_opc_get_ver				= 0x0001,
2288 	ice_aqc_opc_driver_ver				= 0x0002,
2289 	ice_aqc_opc_q_shutdown				= 0x0003,
2290 
2291 	/* resource ownership */
2292 	ice_aqc_opc_req_res				= 0x0008,
2293 	ice_aqc_opc_release_res				= 0x0009,
2294 
2295 	/* device/function capabilities */
2296 	ice_aqc_opc_list_func_caps			= 0x000A,
2297 	ice_aqc_opc_list_dev_caps			= 0x000B,
2298 
2299 	/* manage MAC address */
2300 	ice_aqc_opc_manage_mac_read			= 0x0107,
2301 	ice_aqc_opc_manage_mac_write			= 0x0108,
2302 
2303 	/* PXE */
2304 	ice_aqc_opc_clear_pxe_mode			= 0x0110,
2305 
2306 	/* internal switch commands */
2307 	ice_aqc_opc_get_sw_cfg				= 0x0200,
2308 	ice_aqc_opc_set_port_params			= 0x0203,
2309 
2310 	/* Alloc/Free/Get Resources */
2311 	ice_aqc_opc_alloc_res				= 0x0208,
2312 	ice_aqc_opc_free_res				= 0x0209,
2313 	ice_aqc_opc_share_res				= 0x020B,
2314 	ice_aqc_opc_set_vlan_mode_parameters		= 0x020C,
2315 	ice_aqc_opc_get_vlan_mode_parameters		= 0x020D,
2316 
2317 	/* VSI commands */
2318 	ice_aqc_opc_add_vsi				= 0x0210,
2319 	ice_aqc_opc_update_vsi				= 0x0211,
2320 	ice_aqc_opc_free_vsi				= 0x0213,
2321 
2322 	/* recipe commands */
2323 	ice_aqc_opc_add_recipe				= 0x0290,
2324 	ice_aqc_opc_recipe_to_profile			= 0x0291,
2325 	ice_aqc_opc_get_recipe				= 0x0292,
2326 	ice_aqc_opc_get_recipe_to_profile		= 0x0293,
2327 
2328 	/* switch rules population commands */
2329 	ice_aqc_opc_add_sw_rules			= 0x02A0,
2330 	ice_aqc_opc_update_sw_rules			= 0x02A1,
2331 	ice_aqc_opc_remove_sw_rules			= 0x02A2,
2332 
2333 	ice_aqc_opc_clear_pf_cfg			= 0x02A4,
2334 
2335 	/* DCB commands */
2336 	ice_aqc_opc_query_pfc_mode			= 0x0302,
2337 	ice_aqc_opc_set_pfc_mode			= 0x0303,
2338 
2339 	/* transmit scheduler commands */
2340 	ice_aqc_opc_get_dflt_topo			= 0x0400,
2341 	ice_aqc_opc_add_sched_elems			= 0x0401,
2342 	ice_aqc_opc_cfg_sched_elems			= 0x0403,
2343 	ice_aqc_opc_get_sched_elems			= 0x0404,
2344 	ice_aqc_opc_move_sched_elems			= 0x0408,
2345 	ice_aqc_opc_suspend_sched_elems			= 0x0409,
2346 	ice_aqc_opc_resume_sched_elems			= 0x040A,
2347 	ice_aqc_opc_query_port_ets			= 0x040E,
2348 	ice_aqc_opc_delete_sched_elems			= 0x040F,
2349 	ice_aqc_opc_add_rl_profiles			= 0x0410,
2350 	ice_aqc_opc_query_sched_res			= 0x0412,
2351 	ice_aqc_opc_remove_rl_profiles			= 0x0415,
2352 
2353 	/* PHY commands */
2354 	ice_aqc_opc_get_phy_caps			= 0x0600,
2355 	ice_aqc_opc_set_phy_cfg				= 0x0601,
2356 	ice_aqc_opc_set_mac_cfg				= 0x0603,
2357 	ice_aqc_opc_restart_an				= 0x0605,
2358 	ice_aqc_opc_get_link_status			= 0x0607,
2359 	ice_aqc_opc_set_event_mask			= 0x0613,
2360 	ice_aqc_opc_set_mac_lb				= 0x0620,
2361 	ice_aqc_opc_get_link_topo			= 0x06E0,
2362 	ice_aqc_opc_read_i2c				= 0x06E2,
2363 	ice_aqc_opc_write_i2c				= 0x06E3,
2364 	ice_aqc_opc_set_port_id_led			= 0x06E9,
2365 	ice_aqc_opc_get_port_options			= 0x06EA,
2366 	ice_aqc_opc_set_port_option			= 0x06EB,
2367 	ice_aqc_opc_set_gpio				= 0x06EC,
2368 	ice_aqc_opc_get_gpio				= 0x06ED,
2369 	ice_aqc_opc_sff_eeprom				= 0x06EE,
2370 
2371 	/* NVM commands */
2372 	ice_aqc_opc_nvm_read				= 0x0701,
2373 	ice_aqc_opc_nvm_erase				= 0x0702,
2374 	ice_aqc_opc_nvm_write				= 0x0703,
2375 	ice_aqc_opc_nvm_checksum			= 0x0706,
2376 	ice_aqc_opc_nvm_write_activate			= 0x0707,
2377 	ice_aqc_opc_nvm_update_empr			= 0x0709,
2378 	ice_aqc_opc_nvm_pkg_data			= 0x070A,
2379 	ice_aqc_opc_nvm_pass_component_tbl		= 0x070B,
2380 
2381 	/* PF/VF mailbox commands */
2382 	ice_mbx_opc_send_msg_to_pf			= 0x0801,
2383 	ice_mbx_opc_send_msg_to_vf			= 0x0802,
2384 	/* LLDP commands */
2385 	ice_aqc_opc_lldp_get_mib			= 0x0A00,
2386 	ice_aqc_opc_lldp_set_mib_change			= 0x0A01,
2387 	ice_aqc_opc_lldp_stop				= 0x0A05,
2388 	ice_aqc_opc_lldp_start				= 0x0A06,
2389 	ice_aqc_opc_get_cee_dcb_cfg			= 0x0A07,
2390 	ice_aqc_opc_lldp_set_local_mib			= 0x0A08,
2391 	ice_aqc_opc_lldp_stop_start_specific_agent	= 0x0A09,
2392 	ice_aqc_opc_lldp_filter_ctrl			= 0x0A0A,
2393 	ice_aqc_opc_lldp_execute_pending_mib		= 0x0A0B,
2394 
2395 	/* RSS commands */
2396 	ice_aqc_opc_set_rss_key				= 0x0B02,
2397 	ice_aqc_opc_set_rss_lut				= 0x0B03,
2398 	ice_aqc_opc_get_rss_key				= 0x0B04,
2399 	ice_aqc_opc_get_rss_lut				= 0x0B05,
2400 
2401 	/* Sideband Control Interface commands */
2402 	ice_aqc_opc_neighbour_device_request		= 0x0C00,
2403 
2404 	/* Tx queue handling commands/events */
2405 	ice_aqc_opc_add_txqs				= 0x0C30,
2406 	ice_aqc_opc_dis_txqs				= 0x0C31,
2407 	ice_aqc_opc_cfg_txqs				= 0x0C32,
2408 	ice_aqc_opc_add_rdma_qset			= 0x0C33,
2409 
2410 	/* package commands */
2411 	ice_aqc_opc_download_pkg			= 0x0C40,
2412 	ice_aqc_opc_upload_section			= 0x0C41,
2413 	ice_aqc_opc_update_pkg				= 0x0C42,
2414 	ice_aqc_opc_get_pkg_info_list			= 0x0C43,
2415 
2416 	ice_aqc_opc_driver_shared_params		= 0x0C90,
2417 
2418 	/* Standalone Commands/Events */
2419 	ice_aqc_opc_event_lan_overflow			= 0x1001,
2420 
2421 	/* debug commands */
2422 	ice_aqc_opc_fw_logging				= 0xFF09,
2423 	ice_aqc_opc_fw_logging_info			= 0xFF10,
2424 };
2425 
2426 #endif /* _ICE_ADMINQ_CMD_H_ */
2427