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Searched refs:lower_32_bits (Results 1 – 25 of 670) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/amd/amdkfd/
Dkfd_packet_manager_v9.c64 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_v9()
71 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
75 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_v9()
79 lower_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
123 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_aldebaran()
125 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_aldebaran()
129 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_aldebaran()
133 lower_32_bits(vm_page_table_base_addr); in pm_map_process_aldebaran()
172 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_v9()
197 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_v9()
[all …]
Dkfd_packet_manager_vi.c69 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_vi()
108 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_vi()
133 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_vi()
136 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
186 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
192 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
264 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_vi()
266 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_vi()
Dkfd_mqd_manager_vi.c116 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
130 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
132 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
142 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
184 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
187 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
189 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
215 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
370 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
372 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_v11.c159 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
187 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
230 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
233 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
235 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
256 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
434 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
436 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
438 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
/linux-6.6.21/drivers/firmware/smccc/
Dkvm_guest.c33 val[0] = lower_32_bits(res.a0); in kvm_init_hyp_services()
34 val[1] = lower_32_bits(res.a1); in kvm_init_hyp_services()
35 val[2] = lower_32_bits(res.a2); in kvm_init_hyp_services()
36 val[3] = lower_32_bits(res.a3); in kvm_init_hyp_services()
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c349 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
361 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
369 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
377 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
415 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
436 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
456 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
468 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
910 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
921 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
[all …]
Dsdma_v6_0.c87 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v6_0_ring_init_cond_exec()
198 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
211 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
216 lower_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
263 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v6_0_ring_emit_ib()
268 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
271 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v6_0_ring_emit_ib()
347 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
349 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v6_0_ring_emit_fence()
358 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
[all …]
Dsdma_v5_2.c97 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
183 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
196 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
200 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
245 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_2_ring_emit_ib()
250 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
253 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_2_ring_emit_ib()
329 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
331 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_2_ring_emit_fence()
340 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
[all …]
Dvcn_v2_5.c433 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
444 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
452 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
460 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
518 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
538 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
550 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
942 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
953 lower_32_bits(ring->wptr)); in vcn_v2_5_start_dpg_mode()
[all …]
Dvcn_v3_0.c463 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
474 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
482 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
490 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
526 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
547 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
567 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
579 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1067 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1078 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode()
[all …]
Dsi_dma.c71 while ((lower_32_bits(ring->wptr) & 7) != 5) in si_dma_ring_emit_ib()
155 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start()
219 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
272 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
319 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
320 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
343 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
346 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
386 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ in si_dma_vm_set_pte_pde()
426 amdgpu_ring_write(ring, lower_32_bits(addr)); in si_dma_ring_emit_pipeline_sync()
[all …]
Dsdma_v5_0.c257 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
373 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
386 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
391 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
438 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_0_ring_emit_ib()
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
446 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
524 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
526 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
535 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
[all …]
Dsdma_v2_4.c254 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v2_4_ring_emit_ib()
259 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
312 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
314 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
320 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
448 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
558 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
613 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
667 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v2_4_vm_copy_pte()
669 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v2_4_vm_copy_pte()
[all …]
Dvcn_v1_0.c320 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
332 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
340 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
390 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
402 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
412 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
928 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
939 lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
945 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
946 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
[all …]
Dsdma_v3_0.c428 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v3_0_ring_emit_ib()
433 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
486 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
488 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
494 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
687 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
709 lower_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
830 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring()
885 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v3_0_ring_test_ib()
938 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v3_0_vm_copy_pte()
[all …]
/linux-6.6.21/drivers/pci/controller/mobiveil/
Dpcie-mobiveil.c151 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ib_windows()
157 mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr), in program_ib_windows()
162 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ib_windows()
192 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ob_windows()
203 lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), in program_ob_windows()
208 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ob_windows()
/linux-6.6.21/drivers/iio/test/
Diio-test-format.c211 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
217 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
223 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
229 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
235 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
241 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
247 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
/linux-6.6.21/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgv100.c47 nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd)); in gv100_chan_ramfc_write()
51 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset)); in gv100_chan_ramfc_write()
102 nvkm_wo32(chan->inst, 0x210, lower_32_bits(addr)); in gv100_ectx_bind()
122 nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2)); in gv100_ectx_ce_bind()
188 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1); in gv100_runl_insert_chan()
190 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id); in gv100_runl_insert_chan()
/linux-6.6.21/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgm20b.c73 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
76 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
79 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
95 .code_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
99 .data_dma_base = lower_32_bits(data), in gm20b_pmu_acr_bld_write()
101 .overlay_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
/linux-6.6.21/drivers/pci/controller/
Dpci-xgene.c290 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
294 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
387 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
389 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); in xgene_pcie_setup_ob_reg()
391 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
399 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
448 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); in xgene_pcie_setup_pims()
451 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); in xgene_pcie_setup_pims()
514 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
520 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
/linux-6.6.21/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgm20b.c41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
60 .code_dma_base = lower_32_bits(code), in gm20b_gr_acr_bld_write()
64 .data_dma_base = lower_32_bits(data), in gm20b_gr_acr_bld_write()
/linux-6.6.21/drivers/accel/habanalabs/common/
Dmemory_mgr.c25 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_get()
67 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_release()
86 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_remove_idr_locked()
118 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_put_handle()
185 idr_remove(&mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_alloc()
/linux-6.6.21/drivers/media/pci/pt3/
Dpt3_dma.c52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
/linux-6.6.21/include/linux/
Dgoldfish.h23 gf_iowrite32(lower_32_bits(addr), portl); in gf_write_ptr()
33 gf_iowrite32(lower_32_bits(addr), portl); in gf_write_dma_addr()
/linux-6.6.21/drivers/gpu/drm/i915/gt/uc/
Dintel_gsc_uc_heci_cmd_submit.c29 *cs++ = lower_32_bits(pkt->addr_in); in emit_gsc_heci_pkt()
32 *cs++ = lower_32_bits(pkt->addr_out); in emit_gsc_heci_pkt()
116 *cmd++ = lower_32_bits(pkt->addr_in); in emit_gsc_heci_pkt_nonpriv()
119 *cmd++ = lower_32_bits(pkt->addr_out); in emit_gsc_heci_pkt_nonpriv()

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