| /linux-6.6.21/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | hwmgr_ppt.h | 97 uint8_t lane_width; member
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| D | vega10_hwmgr.c | 1274 bios_pcie_table->entries[i].lane_width); in vega10_setup_default_pcie_table()
4654 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega10_emit_clock_levels() local
4728 lane_width = pptable->PcieLaneCount[i]; in vega10_emit_clock_levels()
4735 (lane_width == 1) ? "x1" : in vega10_emit_clock_levels()
4736 (lane_width == 2) ? "x2" : in vega10_emit_clock_levels()
4737 (lane_width == 3) ? "x4" : in vega10_emit_clock_levels()
4738 (lane_width == 4) ? "x8" : in vega10_emit_clock_levels()
4739 (lane_width == 5) ? "x12" : in vega10_emit_clock_levels()
4740 (lane_width == 6) ? "x16" : "", in vega10_emit_clock_levels()
4742 (current_lane_width == lane_width) ? in vega10_emit_clock_levels()
[all …]
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| D | vega20_hwmgr.c | 3369 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_print_clock_levels() local
3463 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
3470 (lane_width == 1) ? "x1" : in vega20_print_clock_levels()
3471 (lane_width == 2) ? "x2" : in vega20_print_clock_levels()
3472 (lane_width == 3) ? "x4" : in vega20_print_clock_levels()
3473 (lane_width == 4) ? "x8" : in vega20_print_clock_levels()
3474 (lane_width == 5) ? "x12" : in vega20_print_clock_levels()
3475 (lane_width == 6) ? "x16" : "", in vega20_print_clock_levels()
3478 (current_lane_width == lane_width) ? in vega20_print_clock_levels()
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| D | process_pptables_v1_0.c | 519 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
557 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
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| D | vega10_processpptables.c | 815 pcie_table->entries[i].lane_width = in get_pcie_table()
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| D | smu7_hwmgr.c | 677 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
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| /linux-6.6.21/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | arcturus_ppt.c | 769 uint32_t gen_speed, lane_width; in arcturus_print_clk_levels() local
925 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in arcturus_print_clk_levels()
931 (lane_width == 1) ? "x1" : in arcturus_print_clk_levels()
932 (lane_width == 2) ? "x2" : in arcturus_print_clk_levels()
933 (lane_width == 3) ? "x4" : in arcturus_print_clk_levels()
934 (lane_width == 4) ? "x8" : in arcturus_print_clk_levels()
935 (lane_width == 5) ? "x12" : in arcturus_print_clk_levels()
936 (lane_width == 6) ? "x16" : "", in arcturus_print_clk_levels()
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| D | navi10_ppt.c | 1266 uint32_t gen_speed, lane_width; in navi10_emit_clk_levels() local
1337 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in navi10_emit_clk_levels()
1352 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in navi10_emit_clk_levels()
1473 uint32_t gen_speed, lane_width; in navi10_print_clk_levels() local
1537 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in navi10_print_clk_levels()
1552 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in navi10_print_clk_levels()
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| D | sienna_cichlid_ppt.c | 1276 uint32_t gen_speed, lane_width; in sienna_cichlid_print_clk_levels() local
1338 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in sienna_cichlid_print_clk_levels()
1354 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in sienna_cichlid_print_clk_levels()
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| /linux-6.6.21/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | smu_v13_0_7_ppt.c | 1147 uint32_t gen_speed, lane_width; in smu_v13_0_7_print_clk_levels() local
1243 &lane_width); in smu_v13_0_7_print_clk_levels()
1262 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? in smu_v13_0_7_print_clk_levels()
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| D | smu_v13_0_0_ppt.c | 1166 uint32_t gen_speed, lane_width; in smu_v13_0_0_print_clk_levels() local
1262 &lane_width); in smu_v13_0_0_print_clk_levels()
1281 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? in smu_v13_0_0_print_clk_levels()
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| /linux-6.6.21/drivers/gpu/drm/radeon/ |
| D | si_dpm.c | 4681 u32 lane_width; in si_init_smc_table() local
4752 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4753 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
5898 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
5906 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5907 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
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| /linux-6.6.21/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| D | si_dpm.c | 5183 u32 lane_width; in si_init_smc_table() local
5254 lane_width = amdgpu_get_pcie_lanes(adev); in si_init_smc_table()
5255 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
6395 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
6403 lane_width = amdgpu_get_pcie_lanes(adev); in si_set_pcie_lane_width_in_smc()
6404 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
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