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Searched refs:ixSQ_WAVE_STATUS (Results 1 – 22 of 22) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h89 #define ixSQ_WAVE_STATUS 0x0012 macro
Dgfx_7_0_d.h1913 #define ixSQ_WAVE_STATUS 0x12 macro
Dgfx_7_2_d.h1934 #define ixSQ_WAVE_STATUS 0x12 macro
Dgfx_8_0_d.h2133 #define ixSQ_WAVE_STATUS 0x12 macro
Dgfx_8_1_d.h2101 #define ixSQ_WAVE_STATUS 0x12 macro
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_2.c1834 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_2_log_cu_timeout_status()
Dgfx_v9_4_3.c581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
3921 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_log_cu_timeout_status()
Dgfx_v6_0.c2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
Dgfx_v7_0.c4116 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
Dgfx_v11_0.c789 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v11_0_read_wave_data()
Dgfx_v8_0.c5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
Dgfx_v9_0.c1771 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
Dgfx_v10_0.c4280 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h7098 #define ixSQ_WAVE_STATUS macro
Dgc_9_1_offset.h7306 #define ixSQ_WAVE_STATUS macro
Dgc_9_2_1_offset.h7345 #define ixSQ_WAVE_STATUS macro
Dgc_9_4_2_offset.h7646 #define ixSQ_WAVE_STATUS macro
Dgc_9_4_3_offset.h7408 #define ixSQ_WAVE_STATUS macro
Dgc_10_1_0_offset.h11177 #define ixSQ_WAVE_STATUS macro
Dgc_11_0_0_offset.h11638 #define ixSQ_WAVE_STATUS macro
Dgc_11_0_3_offset.h12055 #define ixSQ_WAVE_STATUS macro
Dgc_10_3_0_offset.h13423 #define ixSQ_WAVE_STATUS macro