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Searched refs:ixSQ_WAVE_INST_DW0 (Results 1 – 19 of 19) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h82 #define ixSQ_WAVE_INST_DW0 0x001A macro
Dgfx_7_0_d.h1906 #define ixSQ_WAVE_INST_DW0 0x1a macro
Dgfx_7_2_d.h1927 #define ixSQ_WAVE_INST_DW0 0x1a macro
Dgfx_8_0_d.h2125 #define ixSQ_WAVE_INST_DW0 0x1a macro
Dgfx_8_1_d.h2093 #define ixSQ_WAVE_INST_DW0 0x1a macro
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_2.c1842 wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_4_2_log_cu_timeout_status()
Dgfx_v9_4_3.c587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_4_3_read_wave_data()
3929 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_4_3_log_cu_timeout_status()
Dgfx_v6_0.c2981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v6_0_read_wave_data()
Dgfx_v7_0.c4122 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v7_0_read_wave_data()
Dgfx_v8_0.c5228 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v8_0_read_wave_data()
Dgfx_v9_0.c1777 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_0_read_wave_data()
Dgfx_v10_0.c4287 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); in gfx_v10_0_read_wave_data()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h7106 #define ixSQ_WAVE_INST_DW0 macro
Dgc_9_1_offset.h7314 #define ixSQ_WAVE_INST_DW0 macro
Dgc_9_2_1_offset.h7353 #define ixSQ_WAVE_INST_DW0 macro
Dgc_9_4_2_offset.h7654 #define ixSQ_WAVE_INST_DW0 macro
Dgc_9_4_3_offset.h7416 #define ixSQ_WAVE_INST_DW0 macro
Dgc_10_1_0_offset.h11185 #define ixSQ_WAVE_INST_DW0 macro
Dgc_10_3_0_offset.h13431 #define ixSQ_WAVE_INST_DW0 macro