Searched refs:ixCG_SPLL_FUNC_CNTL (Results 1 – 11 of 11) sorted by relevance
| /linux-6.6.21/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | fiji_baco.c | 59 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
79 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
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| D | ci_baco.c | 61 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
90 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
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| D | polaris_baco.c | 58 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
144 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
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| D | tonga_baco.c | 59 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
81 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
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| D | smu7_hwmgr.c | 4792 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); in smu7_read_clock_registers()
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| /linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_7_0_0_d.h | 45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
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| D | smu_7_1_1_d.h | 45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
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| D | smu_7_0_1_d.h | 45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
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| D | smu_7_1_2_d.h | 45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
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| D | smu_7_1_3_d.h | 48 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
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| D | smu_7_1_0_d.h | 45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
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